1. About this document

This document is an effort to document the SC9830I SoC from the SharkLS SCX35L family from Spreadtrum.

The SC9830I contains 2 dies. The digital die, or d-die, and the analog one, or a-die. The analog die in this SoC is a SC2723.

The information in this document comes only from public sources, such as GPL'd source code, datasheets from other chips using the same IP blocks, and experimentation on real hardware.

Be aware that because of this, this document potentially contains a lot of imprecise, if not downright incorrect information.

2. Memory map

Map of the physical memory and I/O space as seen by the Application Processor.

2.1. Buses

AP address	ARM7 address	Name	Description
0x20000000	?	AP AHB	AHB peripherals for the application processor
0x40000000	0x40000000	Global bus	Low speed APB peripherals and configuration registers shared across cores
0x70000000		AP APB	UART/I2C/I2S for the application processor

2.2. AXI/AHB peripherals

Range	Region size (w/o mirrors)	Description
0x00000000-0x00000fff	0x1000	IRAM0
0x00001000-0x00001fff	0x1000	IRAM0H
0x10000000-0x1000ffff	0x10000	ARM Coresight
0x12000000-0x1200ffff	0x10000	ARM Cortex-A7 peripherals
0x12001000-0x12001fff	0x1000	GIC dist registers
0x12002000-0x12002fff	0x1000	GIC CPU registers
0x20100000-0x20103fff	0x4000	AP DMA
0x20200000-0x20200fff	0x1000	USB
0x20300000-0x20300fff	0x1000	SDIO0
0x20400000-0x20400fff	0x1000	SDIO1
0x20500000-0x20500fff	0x1000	SDIO2
0x20600000-0x20600fff	0x1000	SDIO3/eMMC
0x20700000-0x20700fff	0x1000	DRM
0x20800000-0x20800fff	0x1000	LCDC / FB0
0x20900000-0x20900fff	0x1000	LCDC1
0x20a00000-0x20a00fff	0x1000	GSP (scaler)
0x20b00000-0x20b07fff	0x8000	GSP IOMMU page table
0x20b08000-0x20b0ffff	0x8000	GSP IOMMU control
0x20d00000-0x20d00fff	0x1000	HW spinlock 0
0x20e00000-0x20e0ffff	0x10000	AHB control
0x20f00000-0x20f0????	0x????	AHB bus monitor
0x21200000-0x21200fff	0x1000	ZIP encoder
0x21300000-0x21300fff	0x1000	ZIP decoder
0x21400000-0x2140????	0x????	? (present but unknown)
0x21500000-0x21500fff	0x1000	ABP clock generation
0x21800000-0x21800fff	0x1000	FB1
0x30000000-0x3000ffff	0x1000	LPDDR2
0x30010000-0x3001ffff	0x1000	LPDDR2_PHY
0x30020000-0x3002ffff	0x10000	PUB
0x30040000-0x3005ffff	0x20000	AXI bus monitor 0
0x40000000-0x40001fff	0x2000	AUDIO?
0x40010000-0x40010fff	0x1000	AUDIO_IF?
0x40020000-0x4002ffff	0x10000	VBC r2p0
0x40030000-0x40030fff	0x1000	ADI bus control
0x40038000-0x40038fff	0x1000	ADI bus
0x40040000-0x40040fff	0x1000	SYSTIMER_CMP (check)
0x40050000-0x40050fff	0x1000	GP timer 0
0x40060000-0x40060fff	0x1000	HW spinlock 1
0x40070000-0x40070fff	0x1000	RFSPI (check)
0x400a0000-0x400a0fff	0x1000	Send MBOX
0x400a8000-0x400a8fff	0x1000	Receive MBOX
0x40100000-0x40103fff	0x4000	AON DMA
0x40200000-0x40200fff	0x1000	INT (MUX)\|
0x40210000-0x40210fff	0x1000	EIC GPIO
0x40220000-0x40220fff	0x1000	AP timer 0
0x40230000-0x40230fff	0x1000	SYSCNT
0x40240000-0x40240fff	0x1000	UID eFuse
0x40250000-0x40250fff	0x1000	Keypad
0x40260000-0x40260fff	0x1000	PWM
0x40270000-0x40270fff	0x1000	FM
0x40280000-0x40280fff	0x1000	GPIO GPIO
0x40290000-0x40290fff	0x1000	Watchdog
0x402a0000-0x402a0fff	0x1000	Pin muxing
0x402b0000-0x402bffff	0x10000	Power Management Unit
0x402c0000-0x402c0fff	0x1000	IPI
0x402d0000-0x402d0fff	0x1000	AON clock generation
0x402e0000-0x402effff	0x10000	AON APB control
0x402f0000-0x402f0fff	0x1000	Thermal
0x40310000-0x40310fff	0x1000	Cortex-A7 watchdog
0x40320000-0x40320fff	0x1000	AP timer 1
0x40330000-0x40330fff	0x1000	AP timer 2
0x50000000-0x50002fff	0x3000	IRAM1
0x50004000-0x5000cfff	0x9000	IRAM2
0x5000d000-0x50010fff	0x4000	IRAM3?
0x50800000-0x50800fff	0x1000	scproc_arm7 IRAM?
0x50820000-0x50820fff	0x1000	ARM7AHBRF (check)
0x60000000-0x6000ffff	0x10000	MALI-400 GPU
0x60100000-0x60100fff	0x1000	GPU APB registers
0x60200000-0x60200fff	0x1000	GPU clock generation
0x60800000-0x608fffff	0x100000	DCAM
0x60900000-0x6090bfff	0xc000	VSP
0x60a00000-0x60a0bfff	0xc000	ISP
0x60b00000-0x60b07fff	0x8000	JPG
0x60c00000-0x60cfffff	0x100000	CSI2 (Sensor)
0x60d00000-0x60d03fff	0x4000	MM AHB control
0x60e00000-0x60e00fff	0x1000	MM clock generation
0x60f00000-0x60f1ffff	0x20000	MM IOMMU page table
0x60f20000-0x60f21fff	0x2000	MM IOMMU control
0x61000000-0x61003fff	0x4000	VPP
0x62000000-0x62000fff	0x1000	Codec AHB control?
0x62100000-0x62103fff	0x4000	CODA7L
0x70000000-0x70000fff	0x1000	UART0
0x70100000-0x70100fff	0x1000	UART1
0x70200000-0x70200fff	0x1000	UART2
0x70300000-0x70300fff	0x1000	UART3
0x70400000-0x70400fff	0x1000	UART4
0x70500000-0x70500fff	0x1000	I2C0
0x70600000-0x70600fff	0x1000	I2C1
0x70700000-0x70700fff	0x1000	I2C2
0x70800000-0x70800fff	0x1000	I2C3
0x70900000-0x70900fff	0x1000	I2C4
0x70a00000-0x70a00fff	0x1000	SPI0
0x70b00000-0x70b00fff	0x1000	SPI1
0x70c00000-0x70c00fff	0x1000	SPI2
0x70d00000-0x70dfffff	0x100000	IIS0
0x70e00000-0x70efffff	0x100000	IIS1
0x70f00000-0x70ffffff	0x100000	IIS2
0x71000000-0x710fffff	0x100000	IIS3
0x71100000-0x7110ffff	0x10000	SIM0
0x71300000-0x71301fff	0x2000	AP APB enable and reset
0x71400000-0x71400fff	0x1000	INTC0
0x71500000-0x71500fff	0x1000	INTC1
0x71600000-0x71600fff	0x1000	INTC2
0x71700000-0x71700fff	0x1000	INTC3
0x80000000-0xffefffff	Variable	DDR
0xfff00000-0xfff1ffff	?	Cortex xxx peripherals
0xffff0000-0xffffffff	0x8000	Boot ROM

2.3. GSP AXI bus

0x20000000

2.4. AON (always on) bus

0x40000000

2.5. ADI bus peripherals

0x40038000-0x40038fff

ADI = Analog Die Interconnect?

Range	Region size (w/o mirrors)	Description
0x020-0x03f	0x20	PWM
0x040-0x07f	0x40	Watchdog
0x080-0x0ff	0x80	RTC
0x100-0x17f	0x80	EIC GPIO
0x180-0x???	0x??	PIN
0x200-0x2??	0x??	ANA_EFUSE
0x280-0x2??	0x??	Thermal
0x300-0x37f	0x80	ADC
0x380-0x3bf	0x40	ANA_CTL_INT
0x3c0-0x3ff	0x40	ANA_BTLC_INT
0x400-0x47f	0x80	ANA_AUDIFA_INT
0x480-0x4ff	0x80	GPIO GPIO
0x500-0x5ff	0x100	ANA_FPU_INT
0x600-0x6ff	0x100	ANA_AUDCFGA_INT
0x700-0x7ff	0x100	ANA_HDT_INT
0x800-0x8ff	0x100	ANA_CTL_GLB

2.6. MM AXI bus

0x60000000

2.7. APB peripherals

I/O layout of APB peripherals region.

Range	Region size (w/o mirrors)	Description
0x-0x	0x	SIM0
0x-0x	0x	AP_CKG

2.8. MPCore peripherals

I/O layout of Cortex A9 peripherals region.

Range	Region size (w/o mirrors)	Description
0xfff00000-0xfff000ff	0x100	A9 SCU
0xfff00100-0xfff001ff	0x100?	A9 Interrupt controller INT
0xfff00200-0xfff002ff	0x100?	A9 Global Timer
0xfff00600-0xfff006ff	0x100?	A9 Timer
0xfff01000-0xfff010ff	0x1000	A9 Interrupt controller DIST
0xfff10000-0xfff1ffff	?	L2 cache controller

3. AP AHB control

Base address
0x20e00000

3.1. Registers

Symbol	Offset	Description
AHB_EB	0x0000	AHB enable bits
AHB_RST	0x0004	AHB reset bits
CA7_RST_SET	0x0008
AP_SYS_FORCE_SLEEP_CFG	0x000c
AP_SYS_AUTO_SLEEP_CFG	0x0010
HOLDING_PEN	0x0014
JMP_ADDR_CA7_C0	0x0018
JMP_ADDR_CA7_C1	0x001c
JMP_ADDR_CA7_C2	0x0020
JMP_ADDR_CA7_C3	0x0024
CA7_C0_PU_LOCK	0x0028
CA7_C1_PU_LOCK	0x002c
CA7_C2_PU_LOCK	0x0030
CA7_C3_PU_LOCK	0x0034
CA7_CKG_DIV_CFG	0x0038
MCU_PAUSE	0x003c
MISC_CKG_EN	0x0040
CA7_C0_AUTO_FORCE_SHUTDOWN_EN	0x0044
CA7_C1_AUTO_FORCE_SHUTDOWN_EN	0x0048
CA7_C2_AUTO_FORCE_SHUTDOWN_EN	0x004c
CA7_C3_AUTO_FORCE_SHUTDOWN_EN	0x0050
CA7_CKG_SEL_CFG	0x0054
MISC_CFG	0x3000
AP_MAIN_MTX_HPROT_CFG	0x3004
CA7_STANDBY_STATUS	0x3008
NANC_CLK_CFG	0x300c
LVDS_CFG	0x3010
LVDS_PLL_CFG0	0x3014
LVDS_PLL_CFG1	0x3018
AP_QOS_CFG	0x301c
OTG_PHY_TUNE	0x3020
OTG_PHY_TEST	0x3024
OTG_PHY_CTRL	0x3028
HSIC_PHY_TUNE	0x302c
HSIC_PHY_TEST	0x3030
HSIC_PHY_CTRL	0x3034
ZIP_MTX_QOS_CFG	0x3038
CHIP_ID	0x30fc

3.1.1. AHB_EB (0x20e00000)

Symbol	Bit range	R/W
ZIPMTX_EB	23	RW
LVDS_EB	22	RW
ZIPDEC_EB	21	RW
ZIPENC_EB	20	RW
NANDC_ECC_EB	19	RW
NANDC_2X_EB	18	RW
NANDC_EB	17	RW
BUSMON2_EB	16	RW
BUSMON1_EB	15	RW
BUSMON0_EB	14	RW
SPINLOCK_EB	13	RW
?	12	RW
EMMC_EB	11	RW
SDIO2_EB	10	RW
SDIO1_EB	9	RW
SDIO0_EB	8	RW
DRM_EB	7	RW
NFC_EB	6	RW
DMA_EB	5	RW
OTG_EB	4	RW
GSP_EB	3	RW
HSIC_EB	2	RW
DISPC0_EB	1	RW
DSI_EB	0	RW

3.1.2. AHB_RST (0x20e00004)

Symbol	Bit range	R/W
HSIC_PHY_SOFT_RST	30	RW
HSIC_UTMI_SOFT_RST	29	RW
HSIC_SOFT_RST	28	RW
LVDS_SOFT_RST	25	RW
ZIP_MTX_SOFT_RST	24	RW
ZIPDEC_SOFT_RST	23	RW
ZIPENC_SOFT_RST	22	RW
NANDC_SOFT_RST	20	RW
BUSMON2_SOFT_RST	19	RW
BUSMON1_SOFT_RST	18	RW
BUSMON0_SOFT_RST	17	RW
SPINLOCK_SOFT_RST	16	RW
EMMC_SOFT_RST	14	RW
SDIO2_SOFT_RST	13	RW
SDIO1_SOFT_RST	12	RW
SDIO0_SOFT_RST	11	RW
DRM_SOFT_RST	10	RW
NFC_SOFT_RST	9	RW
DMA_SOFT_RST	8	RW
OTG_PHY_SOFT_RST	6	RW
OTG_UTMI_SOFT_RST	5	RW
OTG_SOFT_RST	4	RW
GSP_SOFT_RST	3	RW
DISP_MTX_SOFT_RST	2	RW
DISPC0_SOFT_RST	1	RW
DSI_SOFT_RST	0	RW

3.1.3. CA7_RST_SET (0x20e00008)

Symbol	Bit range	R/W
CA7_CS_DBG_SOFT_RST	14	RW
CA7_L2_SOFT_RST	13	RW
CA7_SOCDBG_SOFT_RST	12	RW
CA7_ETM_SOFT_RST	11-8	RW
CA7_DBG_SOFT_RST	7-4	RW
CA7_CORE_SOFT_RST	3-0	RW

3.1.4. AP_SYS_FORCE_SLEEP_CFG (0x20e0000c)

Symbol	Bit range	R/W
CA7_C3_AUTO_SLP_EN	15	RW
CA7_C2_AUTO_SLP_EN	14	RW
CA7_C1_AUTO_SLP_EN	13	RW
CA7_C0_AUTO_SLP_EN	12	RW
CA7_C3_WFI_SHUTDOWN_EN	11	RW
CA7_C2_WFI_SHUTDOWN_EN	10	RW
CA7_C1_WFI_SHUTDOWN_EN	9	RW
CA7_C0_WFI_SHUTDOWN_EN	8	RW
MCU_CA7_C3_SLEEP	7	RW
MCU_CA7_C2_SLEEP	6	RW
MCU_CA7_C1_SLEEP	5	RW
MCU_CA7_C0_SLEEP	4	RW
AP_PERI_FORCE_ON	2	RW
AP_PERI_FORCE_SLP	1	RW
AP_APB_SLEEP	0	RW

3.1.5. AP_SYS_AUTO_SLEEP_CFG (0x20e00010)

Symbol	Bit range	R/W
GSP_CKG_FORCE_EN	9	RW
GSP_AUTO_GATE_EN	8	RW
AP_AHB_AUTO_GATE_EN	5	RW
AP_EMC_AUTO_GATE_EN	4	RW
CA7_EMC_AUTO_GATE_EN	3	RW
CA7_DBG_FORCE_SLEEP	2	RW
CA7_DBG_AUTO_GATE_EN	1	RW
CA7_CORE_AUTO_GATE_EN	0	RW

3.1.6. HOLDING_PEN (0x20e00014)

Holding pen for secondary CA7 cores boot

Symbol	Bit range	R/W	Description
HOLDING_PEN	31-0	RW

3.1.7. JMP_ADDR_CA7_C0 (0x20e00018)

Symbol	Bit range	R/W	Description
JMP_ADDR	31-0	RW	AP core 0 boot jump address

3.1.8. JMP_ADDR_CA7_C1 (0x20e0001c)

Symbol	Bit range	R/W	Description
JMP_ADDR	31-0	RW	AP core 1 boot jump address

3.1.9. JMP_ADDR_CA7_C2 (0x20e00020)

Symbol	Bit range	R/W	Description
JMP_ADDR	31-0	RW	AP core 2 boot jump address

3.1.10. JMP_ADDR_CA7_C3 (0x20e00024)

Symbol	Bit range	R/W	Description
JMP_ADDR	31-0	RW	AP core 3 boot jump address

3.1.11. CA7_C0_PU_LOCK (0x20e00028)

Symbol	Bit range	R/W	Description
CA7_C0_PU_LOCK	0	RW

3.1.12. CA7_C1_PU_LOCK (0x20e0002c)

Symbol	Bit range	R/W	Description
CA7_C1_PU_LOCK	0	RW

3.1.13. CA7_C2_PU_LOCK (0x20e00030)

Symbol	Bit range	R/W	Description
CA7_C2_PU_LOCK	0	RW

3.1.14. CA7_C3_PU_LOCK (0x20e00034)

Symbol	Bit range	R/W	Description
CA7_C3_PU_LOCK	0	RW

3.1.15. CA7_CKG_DIV_CFG (0x20e00038)

Symbol	Bit range	R/W
CA7_DBG_CKG_DIV	18-16	RW
CA7_AXI_CKG_DIV	10-8	RW
CA7_MCU_CKG_DIV	6-4	RW

3.1.16. MCU_PAUSE (0x20e0003c)

Symbol	Bit range	R/W
DMA_ACT_LIGHT_EN	5	RW
MCU_SLEEP_FOLLOW_CA7_EN	4	RW
MCU_LIGHT_SLEEP_EN	3	RW
MCU_DEEP_SLEEP_EN	2	RW
MCU_SYS_SLEEP_EN	1	RW
MCU_CORE_SLEEP	0	RW

3.1.17. MISC_CKG_EN (0x20e00040)

Symbol	Bit range	R/W
ASHB_CA7_DBG_VLD	9	RW
ASHB_CA7_DBG_EN	8	RW
DISP_TMC_CKG_EN	4	RW
DPHY_REF_CKG_EN	1	RW
DPHY_CFG_CKG_EN	0	RW

3.1.18. CA7_C0_AUTO_FORCE_SHUTDOWN_EN (0x20e00044)

Symbol	Bit range	R/W	Description
CA7_C0_AUTO_FORCE_SHUTDOWN_EN	0	RW

3.1.19. CA7_C1_AUTO_FORCE_SHUTDOWN_EN (0x20e00048)

Symbol	Bit range	R/W	Description
CA7_C1_AUTO_FORCE_SHUTDOWN_EN	1	RW

3.1.20. CA7_C2_AUTO_FORCE_SHUTDOWN_EN (0x20e0004c)

Symbol	Bit range	R/W	Description
CA7_C2_AUTO_FORCE_SHUTDOWN_EN	2	RW

3.1.21. CA7_C3_AUTO_FORCE_SHUTDOWN_EN (0x20e00050)

Symbol	Bit range	R/W	Description
CA7_C3_AUTO_FORCE_SHUTDOWN_EN	3	RW

3.1.22. CA7_CKG_SEL_CFG (0x20e00054)

Symbol	Bit range	R/W	Description
CA7_MCU_CKG_SEL	2-0	RW

3.1.23. MISC_CFG (0x20e03000)

Symbol	Bit range	R/W
EMMC_SLOT_SEL	19-18	RW
SDIO_SLOT_SEL	17-16	RW
BUSMON2_CHN_SEL	11-10	RW
BUSMON1_CHN_SEL	9-8	RW
BUSMON0_CHN_SEL	5-4	RW
SDIO2_SLOT_SEL	3-2	RW
SDIO1_SLOT_SEL	1-0	RW

3.1.24. AP_MAIN_MTX_HPROT_CFG (0x20e03004)

Symbol	Bit range	R/W	Description
HPROT_NFC	27-24	RW	AHB HPROT value for NFC master accesses
HPROT_EMMC	23-20	RW	AHB HPROT value for EMMC master accesses
HPROT_SDIO2	19-16	RW	AHB HPROT value for SDIO2 master accesses
HPROT_SDIO1	15-12	RW	AHB HPROT value for SDIO1 master accesses
HPROT_SDIO0	11-8	RW	AHB HPROT value for SDIO0 master accesses
HPROT_DMAW	7-4	RW	AHB HPROT value for DMA write master accesses
HPROT_DMAR	3-0	RW	AHB HPROT value for DMA read master accesses

3.1.25. CA7_STANDBY_STATUS (0x20e03008)

Symbol	Bit range	R/W
CA7_STANDBYWFIL2	12	R
CA7_ETMSTANDBYWFX	11-8	R
CA7_STANDBYWFE	7-4	R
CA7_STANDBYWFI	3-0	R

3.1.26. NANC_CLK_CFG (0x20e0300c)

Symbol	Bit range	R/W	Description
CLK_NANDC2X_DIV	3-2	RW
CLK_NANDC2X_SEL	1-0	RW

3.1.27. LVDS_CFG (0x20e03010)

Symbol	Bit range	R/W
LVDS_TXCLKDATA	22-16	RW
LVDS_TXCOM	13-12	RW
LVDS_TXSLEW	11-10	RW
LVDS_TXSW	9-8	RW
LVDS_TXRERSER	7-3	RW
LVDS_PRE_EMP	2-1	RW
LVDS_TXPD	0	RW

3.1.28. LVDS_PLL_CFG0 (0x20e03014)

Symbol	Bit range	R/W
LVDS_PLL_LOCK_DET	31	R
LVDS_PLL_REFIN	25-24	RW
LVDS_PLL_LPF	22-20	RW
LVDS_PLL_DIV_S	18	RW
LVDS_PLL_IBIAS	17-16	RW
LVDS_PLLN	10-0	RW

3.1.29. LVDS_PLL_CFG1 (0x20e03018)

Symbol	Bit range	R/W
LVDS_PLL_KINT	31-12	RW
LVDS_PLL_RSV	9-8	RW
LVDS_PLL_MOD_EN	7	RW
LVDS_PLL_SDM_EN	6	RW
LVDS_PLL_NINT	5-0	RW

3.1.30. AP_QOS_CFG (0x20e0301c)

Symbol	Bit range	R/W
QOS_R_TMC	23-20	RW
QOS_W_TMC	19-16	RW
QOS_R_DISPC	7-4	RW
QOS_W_DISPC	3-0	RW

3.1.31. OTG_PHY_TUNE (0x20e03020)

Symbol	Bit range	R/W
OTG_TXPREEMPPULSETUNE	20	RW?
OTG_TXRESTUNE	19-18	RW
OTG_TXHSXVTUNE	17-16	RW
OTG_TXVREFTUNE	15-12	RW
OTG_TXPREEMPAMPTUNE	11-10	RW
OTG_TXRISETUNE	9-8	RW
OTG_TXFSLSTUNE	7-4	RW
OTG_SQRXTUNE	2-0	RW

3.1.32. OTG_PHY_TEST (0x20e03024)

Symbol	Bit range	R/W
OTG_ATERESET	31	RW
OTG_VBUS_VALID_EXT_SEL	26	RW
OTG_VBUS_VALID_EXT	25	RW
OTG_OTGDISABLE	24	RW
OTG_TESTBURNIN	21	RW
OTG_LOOPBACKENB	20	RW
OTG_TESTDATAOUT	19-16	RW
OTG_VATESTENB	15-14	RW
OTG_TESTCLK	13	RW
OTG_TESTDATAOUTSEL	12	RW
OTG_TESTADDR	11-8	RW
OTG_TESTDATAIN	7-0	RW

3.1.33. OTG_PHY_CTRL (0x20e03028)

Symbol	Bit range	R/W
OTG_SS_SCALEDOWNMODE	26-25	RW
OTG_TXBITSTUFFENH	23	RW
OTG_TXBITSTUFFEN	22	RW
OTG_DMPULLDOWN	21	RW
OTG_DPPULLDOWN	20	RW
OTG_DMPULLUP	9	RW
OTG_COMMONONN	8	RW
OTG_REFCLKSEL	5-4	RW
OTG_FSEL	2-0	RW

3.1.34. HSIC_PHY_TUNE (0x20e0302c)

Symbol	Bit range	R/W
HSIC_REFCLK_DIV	30-24	RW
HSIC_TXPREEMPPULSETUNE	20	RW
HSIC_TXRESTUNE	19-18	RW
HSIC_TXHSXVTUNE	17-16	RW
HSIC_TXVREFTUNE	15-12	RW
HSIC_TXPREEMPAMPTUNE	11-10	RW
HSIC_TXRISETUNE	9-8	RW
HSIC_TXFSLSTUNE	7-4	RW
HSIC_SQRXTUNE	2-0	RW

3.1.35. HSIC_PHY_TEST (0x20e03030)

Symbol	Bit range	R/W
HSIC_ATERESET	31	RW
HSIC_VBUS_VALID_EXT_SEL	26	RW
HSIC_VBUS_VALID_EXT	25	RW
HSIC_OTGDISABLE	24	RW
HSIC_TESTBURNIN	21	RW
HSIC_LOOPBACKENB	20	RW
HSIC_TESTDATAOUT	19-16	RW
HSIC_VATESTENB	15-14	RW
HSIC_TESTCLK	13	RW
HSIC_TESTDATAOUTSEL	12	RW
HSIC_TESTADDR	11-8	RW
HSIC_TESTDATAIN	7-0	RW

3.1.36. HSIC_PHY_CTRL (0x20e03034)

Symbol	Bit range	R/W
HSIC_SS_SCALEDOWNMODE	26-25	RW
HSIC_TXBITSTUFFENH	23	RW
HSIC_TXBITSTUFFEN	22	RW
HSIC_DMPULLDOWN	21	RW
HSIC_DPPULLDOWN	20	RW
HSIC_IF_MODE	16	RW
IF_SELECT_HSIC	13	RW
HSIC_DBNCE_FLTR_BYPASS	12	RW
HSIC_DMPULLUP	9	RW
HSIC_COMMONONN	8	RW
HSIC_REFCLKSEL	5-4	RW
HSIC_FSEL	2-0	RW

3.1.37. ZIP_MTX_QOS_CFG (0x20e03038)

Symbol	Bit range	R/W
ZIPMTX_S0_ARQOS	23-20	RW
ZIPMTX_S0_AWQOS	19-16	RW
ZIPDEC_ARQOS	15-12	RW
ZIPDEC_AWQOS	11-8	RW
ZIPENC_ARQOS	7-4	RW
ZIPENC_AWQOS	3-0	RW

3.1.38. CHIP_ID (0x20e030fc)

Symbol	Bit range	R/W	Description
CHIP_ID	31-0	R	For SCX35L/SC9830I: 0x96300000

4. PUB APB control

Base address
0x30020000

4.1. Registers

Symbol	Offset	Description
BUSMON_CNT_START	0x0000
BUSMON_CFG	0x0004
DDR_EB	0x0008
DDR_SOFT_RST	0x000c
DDR_QOS_CFG1	0x0010
DDR_QOS_CFG2	0x0014
DDR_QOS_CFG3	0x0018
DDR_MRR_STATUS	0x001c
DDR_ID2QOS_SEL	0x003c
DDR_ID2QOS_RCFG0	0x0040
DDR_ID2QOS_RCFG1	0x0044
DDR_ID2QOS_RCFG2	0x0048
DDR_ID2QOS_RCFG3	0x004c
DDR_ID2QOS_RCFG4	0x0050
DDR_ID2QOS_RCFG5	0x0054
DDR_ID2QOS_RCFG6	0x0058
DDR_ID2QOS_RCFG7	0x005c
DDR_ID2QOS_RCFG8	0x0060
DDR_ID2QOS_RCFG9	0x0064
DDR_ID2QOS_WCFG0	0x0080
DDR_ID2QOS_WCFG1	0x0084
DDR_ID2QOS_WCFG2	0x0088
DDR_ID2QOS_WCFG3	0x008c
DDR_ID2QOS_WCFG4	0x0090
DDR_ID2QOS_WCFG5	0x0094
DDR_ID2QOS_WCFG6	0x0098
DDR_ID2QOS_WCFG7	0x009c
DDR_ID2QOS_WCFG8	0x00a0
DDR_ID2QOS_WCFG9	0x00a4
DFI_TIMEOUT_CFG	0x0100
DFI_TIMEOUT_STATUS	0x0104
DFI_TIMEOUT_EN_CNT	0x0108
DFI_TIMEOUT_VALID_CNT	0x010c
DMC_PORT_REMAP_EN	0x3000
DMC_PORTS_MPU_EN	0x3004
DMC_PORT0_ADDR_REMAP	0x3008
DMC_PORT1_ADDR_REMAP	0x300c
DMC_PORT2_ADDR_REMAP	0x3010
DMC_PORT3_ADDR_REMAP	0x3014
DMC_PORT4_ADDR_REMAP	0x3018
DMC_PORT5_ADDR_REMAP	0x301c
DMC_PORT6_ADDR_REMAP	0x3020
DMC_PORT7_ADDR_REMAP	0x3024
DMC_PORT8_ADDR_REMAP	0x3028
DMC_PORT9_ADDR_REMAP	0x302c
DMC_PORT0_MPU_RANGE	0x3030
DMC_PORT1_MPU_RANGE	0x3034
DMC_PORT2_MPU_RANGE	0x3038
DMC_PORT3_MPU_RANGE	0x303c
DMC_PORT4_MPU_RANGE	0x3040
DMC_PORT5_MPU_RANGE	0x3044
DMC_PORT6_MPU_RANGE	0x3048
DMC_PORT7_MPU_RANGE	0x3050
DMC_PORT8_MPU_RANGE	0x3054
DMC_PORT9_MPU_RANGE	0x3058
DMC_PORT0_DUMP_ADDR	0x305c
DMC_PORT1_DUMP_ADDR	0x3060
DMC_PORT2_DUMP_ADDR	0x3064
DMC_PORT3_DUMP_ADDR	0x3068
DMC_PORT4_DUMP_ADDR	0x306c
DMC_PORT5_DUMP_ADDR	0x3070
DMC_PORT6_DUMP_ADDR	0x3074
DMC_PORT7_DUMP_ADDR	0x3078
DMC_PORT8_DUMP_ADDR	0x307c
DMC_PORT9_DUMP_ADDR	0x3080

4.1.1. BUSMON_CNT_START (0x30020000)

Symbol	Bit range	R/W	Description
PUB_BUSMON_CNT_START	0	RW

4.1.2. BUSMON_CFG (0x30020004)

Symbol	Bit range	R/W
PUB_BUSMON9_EB	25	RW
PUB_BUSMON8_EB	24	RW
PUB_BUSMON7_EB	23	RW
PUB_BUSMON6_EB	22	RW
PUB_BUSMON5_EB	21	RW
PUB_BUSMON4_EB	20	RW
PUB_BUSMON3_EB	19	RW
PUB_BUSMON2_EB	18	RW
PUB_BUSMON1_EB	17	RW
PUB_BUSMON0_EB	16	RW
PUB_BUSMON9_SOFT_RST	9	RW
PUB_BUSMON8_SOFT_RST	8	RW
PUB_BUSMON7_SOFT_RST	7	RW
PUB_BUSMON6_SOFT_RST	6	RW
PUB_BUSMON5_SOFT_RST	5	RW
PUB_BUSMON4_SOFT_RST	4	RW
PUB_BUSMON3_SOFT_RST	3	RW
PUB_BUSMON2_SOFT_RST	2	RW
PUB_BUSMON1_SOFT_RST	1	RW
PUB_BUSMON0_SOFT_RST	0	RW

4.1.3. DDR_EB (0x30020008)

Appears unused.

Symbol	Bit range	R/W	Description

4.1.4. DDR_SOFT_RST (0x3002000c)

Appears unused.

Symbol	Bit range	R/W	Description

4.1.5. DDR_QOS_CFG1 (0x30020010)

Symbol	Bit range	R/W
DMC_ARQOS_3	31-28	RW
DMC_AWQOS_3	27-24	RW
DMC_ARQOS_2	23-20	RW
DMC_AWQOS_2	19-16	RW
DMC_ARQOS_1	15-12	RW
DMC_AWQOS_1	11-8	RW
DMC_ARQOS_0	7-4	RW
DMC_AWQOS_0	3-0	RW

4.1.6. DDR_QOS_CFG2 (0x30020014)

Symbol	Bit range	R/W
DMC_ARQOS_7	31-28	RW
DMC_AWQOS_7	27-24	RW
DMC_ARQOS_6	23-20	RW
DMC_AWQOS_6	19-16	RW
DMC_ARQOS_5	15-12	RW
DMC_AWQOS_5	11-8	RW
DMC_ARQOS_4	7-4	RW
DMC_AWQOS_4	3-0	RW

4.1.7. DDR_QOS_CFG3 (0x30020018)

Symbol	Bit range	R/W
DMC_ARQOS_9	15-12	RW
DMC_AWQOS_9	11-8	RW
DMC_ARQOS_8	7-4	RW
DMC_AWQOS_8	3-0	RW

4.1.8. DDR_MRR_STATUS (0x3002001c)

Symbol	Bit range	R/W	Description
		RW

4.1.9. (0x3002xxxx)

Symbol	Bit range	R/W	Description
		RW

5. ANA_EFUSE

eFuse OTP memory on analog die (ADIE).

Base address
0x40380200

5.1. Registers

Symbol	Offset	Description
GLB_CTRL	0x0000	Global control register
DATA_RD	0x0004	Data read register
DATA_WR	0x0008	Data write register
BLOCK_INDEX	0x000c	eFuse block index register
MODE_CTRL	0x0010	eFuse operation mode
STATUS	0x0014	Status register
WR_TIMING_CTRL	0x0028	Write timings register
RD_TIMING_CTRL	0x002c	Read timings register
EFUSE_DEB_CTRL	0x0030	eFuse debug register

5.1.1. GLB_CTRL (0x40380200)

Global control register

Symbol	Bit range	R/W	Description
EFUSE_TYPE	2-1	RW	Efuse type select, 00:TSMC, 01, 1x reserved.
EFUSE_PGM_EN	0	RW	Efuse SW programme enable.

5.1.2. DATA_RD (0x40380204)

Symbol	Bit range	R/W	Description
EFUSE_DATA_RD	7-0	RW	Data byte read from eFuse block

5.1.3. DATA_WR (0x40380208)

Symbol	Bit range	R/W	Description
EFUSE_DATA_WR	7-0	RW	Data byte to write to eFuse block when programming is enabled

5.1.4. BLOCK_INDEX (0x4038020c)

Symbol	Bit range	R/W	Description
READ_WRITE_INDEX	4-0	RW	Index of eFuse block

5.1.5. MODE_CTRL (0x40380210)

Symbol	Bit range	R/W	Description
STANDBY_START	2	W	Enter standby mode
RD_START	1	W	Enter read mode
PG_MODE	0	W	Write 1 to this bit start A_PGM mode(array PGM mode). This bit is self-clear, read this bit will always get 0.

5.1.6. STATUS (0x40380214)

Symbol	Bit range	R/W
STANDBY_BUSY	2	R
READ_BUSY	1	R
PGM_BUSY	0	R

5.1.7. WR_TIMING (0x40380228)

Symbol	Bit range	R/W	Description
EFUSE_WR_TIMING	13-0	RW

5.1.8. RD_TIMING (0x4038022c)

Symbol	Bit range	R/W	Description
EFUSE_RD_TIMING	9-0	RW

5.1.9. EFUSE_DEB_CTRL (0x40380230)

Symbol	Bit range	R/W	Description
MARGIN_MODE_EN	1	RW
DOUBLE_BIT_DISABLE	0	RW	Disable double bit redundency?

6. SYSCNT

Base address
0x40230000

6.1. Registers

Symbol	Offset	Description
ALARM	0x0000
COUNT	0x0004
CTL	0x0008
SHADOW_CNT	0x000c

6.1.1. ALARM (0x40230000)

Symbol	Bit range	R/W	Description
ALARM	31-0	RW	Alarm counter value

6.1.2. COUNT (0x40230004)

Symbol	Bit range	R/W	Description
COUNT	31-0	RW?

6.1.3. CTL (0x40230008)

Symbol	Bit range	R/W	Description
INT_ACK	8	RW?	Write 1 to acknowledge alarm interrupt
ALARM_ENABLE	0	RW?	0=alarm interrupt disabled 1=alarm interrupt enabled

6.1.4. SHADOW_CNT (0x4023000c)

Symbol	Bit range	R/W	Description
COUNT	31-0	RW?	Count value

7. EFUSE

Base address
0x40240000

7.1. Registers

Symbol	Offset	Description
DATA_RD	0x0000	Data read register
DATA_WR	0x0004	Data write register
READ_WRITE_INDEX	0x0008	Index register
MODE_CTRL	0x000c	Operation mode control
CFG0	0x0010	Configuration register 0
CFG1	0x0014	Configuration register 1
STATUS	0x0020	Status register
BLK_FLAG0	0x0024
BLK_FLAG1	0x0028
BLK_FLAG0_CLR	0x0030
BLK_FLAG1_CLR	0x0034
MAGIC_NUMBER	0x0040	Magic number register
STROBE_LOW_WIDTH	0x0044
EFUSE_DEB_CTRL	0x0048	Debug control register

7.1.1. DATA_RD (0x40240000)

Data read from eFuse block.

Symbol	Bit range	R/W	Description
DATA	31-0	R	Last data word read from eFuse

7.1.2. DATA_WR (0x40240004)

Data write register.

Symbol	Bit range	R/W	Description
DATA	31-0	R	Data word to program to eFuse

7.1.3. READ_WRITE_INDEX (0x40240008)

eFuse block index register.

Symbol	Bit range	R/W	Description
READ_WRITE_INDEX	4-0	RW	Index of eFuse block to read/program. 0-15 for user fuses. 16-31 for unknown purpose.

7.1.4. MODE_CTRL (0x4024000c)

Operation mode control.

Symbol	Bit range	R/W	Description
STANDBY_START	2	W	Write 1 to enter standby
RD_START	1	W	Write 1 to enter read mode
PGM_START	0	W	Write 1 to this bit to start A_PGM mode (array PGM mode). This bit is self-clear, read this bit will always get 0.

7.1.5. CFG0 (0x40240010)

Configuration register 0.

Symbol	Bit range	R/W	Description
PGM_EN	31	RW	Only set this bit can SW write register field of TPGM_TIME_CNT and start PGM mode, for protect SW unexpectedly programmed eFuse memory.
EFS_VDD_ON	30	RW	Set this bit will open 0.9v static power supply for efuse memory, before any operation towards to efuse memory this bit have to set to 1. Once this bit is cleared, the efuse will go to power down mode.
BIT_EFS_VDDQ_K2_ON	29	RW
BIT_EFS_VDDQ_K1_ON	28	RW
EFS_TYPE	17-16	RW	eFuse type. 0=? 1=? 2=? 3=?
TPGM_TIME_CNT	8-0	RW

7.1.6. CFG1 (0x40240014)

Configuration register 1.

Symbol	Bit range	R/W	Description
BLK0_AUTO_TEST_EN	0	RW

7.1.7. STATUS (0x40240020)

Symbol	Bit range	R/W
STANDBY_BUSY	2	R
READ_BUSY	1	R
PGM_BUSY	0	R

7.1.8. BLK_FLAG0 (0x40240024)

Symbol	Bit range	R/W	Description
BLK0_PROT_FLAG	0	R

7.1.9. BLK_FLAG1 (0x40240028)

Symbol	Bit range	R/W	Description
BLK0_ERR_FLAG	0	R

7.1.10. BLK_FLAG0_CLR (0x40240030)

Symbol	Bit range	R/W	Description
BLK0_PROT_FLAG_CLR	0	W

7.1.11. BLK_FLAG1_CLR (0x40240034)

Symbol	Bit range	R/W	Description
BLK0_ERR_FLAG_CLR	0	W

7.1.12. MAGIC_NUMBER (0x40240040)

Symbol	Bit range	R/W	Description
DEB_MAGIC_NUMBER	31-16	RW	Write 0x6868 to enable debug features.
MAGIC_NUMBER	15-0	RW	Magic number, only when this field is 0x8810, the efuse programming command can be handle. So, if SW want to program efuse memory, except open clocks and power, the follow conditions must be met: 1. PGM_EN = 1; 2. EFUSE_MAGIC_NUMBER = 0x8810

7.1.13. STROBE_LOW_WIDTH (0x40240044)

Symbol	Bit range	R/W	Description
CLK_EFS_DIV	23-16	RW
EFUSE_STROBE_LOW_WIDTH	7-0	RW

7.1.14. EFUSE_DEB_CTRL (0x40240048)

Debug control register.

I guess this register only takes effect if 0x6868 is written into DEB_MAGIC_NUMBER.

Symbol	Bit range	R/W	Description
MARGIN_MODE_EN	1	RW
DOUBLE_BIT_DISABLE	0	RW	Disable eFuse bits redundancy?

8. Keypad

Instance	Base address
Keypad	0x40250000

8.1. Registers

Symbol	Offset	Description
CTRL	0x00
INT_EN	0x04
INT_RAW_STATUS	0x08
INT_MASK_STATUS	0x0c
INT_CLR	0x10
POLARITY	0x18
DEBOUNCE_CNT	0x1c
LONG_KEY_CNT	0x20
SLEEP_CNT	0x24
CLK_DIV_CNT	0x28
KEY_STATUS	0x2c
SLEEP_STATUS	0x30
DEBUG_STATUS1	0x34
DEBUG_STATUS2	0x38

8.1.1. CTRL (0x40250000)

Symbol	Bit range	R/W	Description
ROW_MSK	23-16	RW	Enable rows 0 - 7
COL_MSK	15-8	RW	Enable cols 0 - 7
LONG_KEY_EN	2	RW
SLEEP_EN	1	RW
EN	0	RW

8.1.2. INT_EN (0x40250004)

Symbol	Bit range	R/W
LONG_KEY_INT3	11	RW
LONG_KEY_INT2	10	RW
LONG_KEY_INT1	9	RW
LONG_KEY_INT0	8	RW
RELEASE_INT3	7	RW
RELEASE_INT2	6	RW
RELEASE_INT1	5	RW
RELEASE_INT0	4	RW
PRESS_INT3	3	RW
PRESS_INT2	2	RW
PRESS_INT1	1	RW
PRESS_INT0	0	RW

8.1.3. INT_RAW_STATUS (0x40250008)

Symbol	Bit range	R/W
LONG_KEY_INT3	11	R
LONG_KEY_INT2	10	R
LONG_KEY_INT1	9	R
LONG_KEY_INT0	8	R
RELEASE_INT3	7	R
RELEASE_INT2	6	R
RELEASE_INT1	5	R
RELEASE_INT0	4	R
PRESS_INT3	3	R
PRESS_INT2	2	R
PRESS_INT1	1	R
PRESS_INT0	0	R

8.1.4. INT_MASK_STATUS (0x4025000c)

Symbol	Bit range	R/W
LONG_KEY_INT3	11	R
LONG_KEY_INT2	10	R
LONG_KEY_INT1	9	R
LONG_KEY_INT0	8	R
RELEASE_INT3	7	R
RELEASE_INT2	6	R
RELEASE_INT1	5	R
RELEASE_INT0	4	R
PRESS_INT3	3	R
PRESS_INT2	2	R
PRESS_INT1	1	R
PRESS_INT0	0	R

8.1.5. INT_CLR (0x40250010)

Symbol	Bit range	R/W
LONG_KEY_INT3	11	RW
LONG_KEY_INT2	10	RW
LONG_KEY_INT1	9	RW
LONG_KEY_INT0	8	RW
RELEASE_INT3	7	RW
RELEASE_INT2	6	RW
RELEASE_INT1	5	RW
RELEASE_INT0	4	RW
PRESS_INT3	3	RW
PRESS_INT2	2	RW
PRESS_INT1	1	RW
PRESS_INT0	0	RW

8.1.6. POLARITY (0x40250018)

Symbol	Bit range	R/W	Description
CFG_COL_POLARITY	31-16	RW
CFG_ROW_POLARITY	15-0	RW

8.1.7. DEBOUNCE_CNT (0x4025001c)

Symbol	Bit range	R/W	Description
DEBOUNCE_CNT	?	RW

8.1.8. LONG_KEY_CNT (0x40250020)

Symbol	Bit range	R/W	Description
LONG_KEY_CNT	?	RW

8.1.9. SLEEP_CNT (0x40250024)

From X ms to SLEEP_CNT value (with CLK_DIV_CNT = 1): (X * 32.768 - 1)

Symbol	Bit range	R/W	Description
SLEEP_CNT	?	RW

8.1.10. CLK_DIV_CNT (0x40250028)

Symbol	Bit range	R/W	Description
CLK_DIV_CNT	?	RW

8.1.11. KEY_STATUS (0x4025002c)

Symbol	Bit range	R/W
INT3_DOWN	31	RW
INT3_ROW	30-28	RW
INT3_COL	26-24	RW
INT2_DOWN	23	RW
INT2_ROW	22-20	RW
INT2_COL	18-16	RW
INT1_DOWN	15	RW
INT1_ROW	14-12	RW
INT1_COL	10-8	RW
INT0_DOWN	7	RW
INT0_ROW	6-4	RW
INT0_COL	2-0	RW

8.1.12. SLEEP_STATUS (0x40250030)

Symbol	Bit range	R/W	Description
SLEEP_STATUS	?	R

8.1.13. DEBUG_STATUS1 (0x40250034)

Symbol	Bit range	R/W	Description
DEBUG_STATUS1	?	R

8.1.14. DEBUG_STATUS2 (0x40250038)

Symbol	Bit range	R/W	Description
DEBUG_STATUS2	?	R

9. PMU

Base address
0x402b0000

9.1. Registers

Symbol	Offset	Description
PD_CA7_TOP_CFG	0x0000	Cortex-A7 top power down config
PD_CA7_C0_CFG	0x0004	Cortex-A7 core 0 power down config
PD_CA7_C1_CFG	0x0008	Cortex-A7 core 1 power down config
PD_CA7_C2_CFG	0x000c	Cortex-A7 core 2 power down config
PD_CA7_C3_CFG	0x0010	Cortex-A7 core 3 power down config
PD_AP_SYS_CFG	0x0018	AP_SYS power down config
PD_MM_TOP_CFG	0x001c	MM_TOP power down config
PD_GPU_TOP_CFG	0x0020	GPU_TOP power down config
PD_CP0_ARM9_0_CFG	0x0024	CP0 ARM9 0 power down config
PD_CP0_ARM9_1_CFG	0x0028	CP0 ARM9 1 power down config
PD_CP0_HU3GE_CFG	0x002c	CP0 HU3GE power down config
PD_CP0_GSM_0_CFG	0x0030	CP0 GSM 0 power down config
PD_CP0_GSM_1_CFG	0x0034	CP0 GSM 1 power down config
PD_CP0_TD_CFG	0x0038	CP0 TD power down config
PD_CP0_CEVA_0_CFG	0x003c	CP0 CEVA DSP 0 power down config
PD_CP0_CEVA_1_CFG	0x0040	CP0 CEVA DSP 1 power down config
PD_CP0_SYS_CFG	0x0044	CP0_SYS power down config
PD_CP1_CA5_CFG	0x0048	CP1 Cortex-A5 power down config
PD_CP1_LTE_P1_CFG	0x004c	CP1 LTE P1 power down config
PD_CP1_LTE_P2_CFG	0x0050	CP1 LTE P2 power down config
PD_CP1_CEVA_CFG	0x0054	CP1 CEVA DSP power down config
PD_CP1_COMWRAP_CFG	0x0058	CP1 COMWRAP power down config
PD_PUB_SYS_CFG	0x005c	PUB_SYS power down config
AP_WAKEUP_POR_CFG	0x0060
XTL_WAIT_CNT	0x0070
XTLBUF_WAIT_CNT	0x0074
PLL_WAIT_CNT1	0x0078
PLL_WAIT_CNT2	0x007c
XTL0_REL_CFG	0x0080
XTL1_REL_CFG	0x0084
XTLBUF0_REL_CFG	0x008c
XTLBUF1_REL_CFG	0x0090
MPLL_REL_CFG	0x0094
DPLL_REL_CFG	0x0098
LTEPLL_REL_CFG	0x009c
TWPLL_REL_CFG	0x00a0
LVDSDIS_PLL_REL_CFG	0x00a4
CP_SOFT_RST	0x00b0	Communication processor soft reset
CP_SLP_STATUS_DBG0	0x00b4
PWR_STATUS0_DBG	0x00bc
PWR_STATUS1_DBG	0x00c0
PWR_STATUS2_DBG	0x00c4
SLEEP_CTRL	0x00cc
DDR_SLEEP_CTRL	0x00d0
SLEEP_STATUS	0x00d4
CA7_TOP_CFG	0x00e4
CA7_C0_CFG	0x00e8
CA7_C1_CFG	0x00ec
CA7_C2_CFG	0x00f0
CA7_C3_CFG	0x00f4
DDR_CHN_SLEEP_CTRL0	0x00f8
DDR_CHN_SLEEP_CTRL1	0x00fc
DDR_OP_MODE_CFG	0x012c
DDR_PHY_RET_CFG	0x0130
26M_SEL_CFG	0x0134
BISR_DONE_STATUS	0x0138
BISR_BUSY_STATUS	0x013c
BISR_BYP_CFG	0x0140
BISR_EN_CFG	0x0144
CGM_AUTO_GATE_SEL_CFG0	0x0148
CGM_AUTO_GATE_SEL_CFG1	0x014c
CGM_AUTO_GATE_SEL_CFG2	0x0150
CGM_AUTO_GATE_SEL_CFG3	0x0154
CGM_FORCE_EN_CFG0	0x0158
CGM_FORCE_EN_CFG1	0x015c
CGM_FORCE_EN_CFG2	0x0160
CGM_FORCE_EN_CFG3	0x0164
SLEEP_XTLON_CTRL	0x0168
MEM_SLP_CFG	0x016c
MEM_SD_CFG	0x0170
CA7_CORE_PU_LOCK	0x0174
ARM7_HOLD_CGM_EN	0x0178
PWR_CNT_WAIT_CFG0	0x017c
PWR_CNT_WAIT_CFG1	0x0180
RC0_REL_CFG	0x0184
RC1_REL_CFG	0x0188
RC_CNT_WAIT_CFG	0x018c
MEM_AUTO_SLP_CFG	0x0190
MEM_AUTO_SD_CFG	0x0194
CP0_PD_SHUTDOWN_CFG	0x0198
CP1_PD_SHUTDOWN_CFG	0x019c
WAKEUP_LOCK_EN	0x01a0
PD_CODEC_TOP_CFG	0x01a4
PD_CA7_C0_SHUTDOWN_MARK_STATUS	0x3000
PD_CA7_C1_SHUTDOWN_MARK_STATUS	0x3004
PD_CA7_C2_SHUTDOWN_MARK_STATUS	0x3008
PD_CA7_C3_SHUTDOWN_MARK_STATUS	0x300c
PD_CA7_TOP_SHUTDOWN_MARK_STATUS	0x3010
PD_AP_SYS_SHUTDOWN_MARK_STATUS	0x3014
PD_GPU_TOP_SHUTDOWN_MARK_STATUS	0x3018
PD_MM_TOP_SHUTDOWN_MARK_STATUS	0x301c
PD_CP0_ARM9_0_SHUTDOWN_MARK_STATUS	0x3020
PD_CP0_ARM9_1_SHUTDOWN_MARK_STATUS	0x3024
PD_CP0_CEVA_0_SHUTDOWN_MARK_STATUS	0x3028
PD_CP0_CEVA_1_SHUTDOWN_MARK_STATUS	0x302c
PD_CP0_GSM_0_SHUTDOWN_MARK_STATUS	0x3030
PD_CP0_GSM_1_SHUTDOWN_MARK_STATUS	0x3034
PD_CP0_TD_SHUTDOWN_MARK_STATUS	0x3038
PD_CP0_HU3GE_SHUTDOWN_MARK_STATUS	0x303c
PD_CP1_CA5_SHUTDOWN_MARK_STATUS	0x3040
PD_CP1_CEVA_SHUTDOWN_MARK_STATUS	0x3044
PD_CP1_LTE_P1_SHUTDOWN_MARK_STATUS	0x3048
PD_CP1_LTE_P2_SHUTDOWN_MARK_STATUS	0x304c
PD_CP1_COMWRAP_SHUTDOWN_MARK_STATUS	0x3050
PD_PUB_SYS_SHUTDOWN_MARK_STATUS	0x3054
PD_CODEC_TOP_SHUTDOWN_MARK_STATUS	0x3058

9.1.1. PD_CA7_TOP_CFG (0x402b0000)

Symbol	Bit range	R/W
DBG_SHUTDOWN_EN	28	RW
FORCE_SHUTDOWN	25	RW
AUTO_SHUTDOWN_EN	24	RW
PWR_ON_DLY	23-16	RW
PWR_ON_SEQ_DLY	15-8	RW
ISO_ON_DLY	7-0	RW

9.1.2. PD_CA7_C0_CFG (0x402b0004)

Symbol	Bit range	R/W
WFI_SHUTDOWN_EN	29	RW
DBG_SHUTDOWN_EN	28	RW
FORCE_SHUTDOWN	25	RW
AUTO_SHUTDOWN_EN	24	RW
PWR_ON_DLY	23-16	RW
PWR_ON_SEQ_DLY	15-8	RW
ISO_ON_DLY	7-0	RW

9.1.3. PD_CA7_C1_CFG (0x402b0008)

Symbol	Bit range	R/W
WFI_SHUTDOWN_EN	29	RW
DBG_SHUTDOWN_EN	28	RW
FORCE_SHUTDOWN	25	RW
AUTO_SHUTDOWN_EN	24	RW
PWR_ON_DLY	23-16	RW
PWR_ON_SEQ_DLY	15-8	RW
ISO_ON_DLY	7-0	RW

9.1.4. PD_CA7_C2_CFG (0x402b000c)

Symbol	Bit range	R/W
WFI_SHUTDOWN_EN	29	RW
DBG_SHUTDOWN_EN	28	RW
FORCE_SHUTDOWN	25	RW
AUTO_SHUTDOWN_EN	24	RW
PWR_ON_DLY	23-16	RW
PWR_ON_SEQ_DLY	15-8	RW
ISO_ON_DLY	7-0	RW

9.1.5. PD_CA7_C3_CFG (0x402b0010)

Symbol	Bit range	R/W
WFI_SHUTDOWN_EN	29	RW
DBG_SHUTDOWN_EN	28	RW
FORCE_SHUTDOWN	25	RW
AUTO_SHUTDOWN_EN	24	RW
PWR_ON_DLY	23-16	RW
PWR_ON_SEQ_DLY	15-8	RW
ISO_ON_DLY	7-0	RW

9.1.6. PD_AP_SYS_CFG (0x402b0018)

Symbol	Bit range	R/W
FORCE_SHUTDOWN	25	RW
AUTO_SHUTDOWN_EN	24	RW
PWR_ON_DLY	23-16	RW
PWR_ON_SEQ_DLY	15-8	RW
ISO_ON_DLY	7-0	RW

9.1.7. PD_MM_TOP_CFG (0x402b001c)

Symbol	Bit range	R/W
FORCE_SHUTDOWN	25	RW
AUTO_SHUTDOWN_EN	24	RW
PWR_ON_DLY	23-16	RW
PWR_ON_SEQ_DLY	15-8	RW
ISO_ON_DLY	7-0	RW

9.1.8. PD_GPU_TOP_CFG (0x402b0020)

Symbol	Bit range	R/W
FORCE_SHUTDOWN	25	RW
AUTO_SHUTDOWN_EN	24	RW
PWR_ON_DLY	23-16	RW
PWR_ON_SEQ_DLY	15-8	RW
ISO_ON_DLY	7-0	RW

9.1.9. PD_CP0_ARM9_0_CFG (0x402b0024)

Symbol	Bit range	R/W
FORCE_SHUTDOWN	25	RW
AUTO_SHUTDOWN_EN	24	RW
PWR_ON_DLY	23-16	RW
PWR_ON_SEQ_DLY	15-8	RW
ISO_ON_DLY	7-0	RW

9.1.10. PD_CP0_ARM9_1_CFG (0x402b0028)

Symbol	Bit range	R/W
FORCE_SHUTDOWN	25	RW
AUTO_SHUTDOWN_EN	24	RW
PWR_ON_DLY	23-16	RW
PWR_ON_SEQ_DLY	15-8	RW
ISO_ON_DLY	7-0	RW

9.1.11. PD_CP0_HU3GE_CFG (0x402b002c)

Symbol	Bit range	R/W
FORCE_SHUTDOWN	25	RW
AUTO_SHUTDOWN_EN	24	RW
PWR_ON_DLY	23-16	RW
PWR_ON_SEQ_DLY	15-8	RW
ISO_ON_DLY	7-0	RW

9.1.12. PD_CP0_GSM_0_CFG (0x402b0030)

Symbol	Bit range	R/W
FORCE_SHUTDOWN	25	RW
AUTO_SHUTDOWN_EN	24	RW
PWR_ON_DLY	23-16	RW
PWR_ON_SEQ_DLY	15-8	RW
ISO_ON_DLY	7-0	RW

9.1.13. PD_CP0_GSM_1_CFG (0x402b0034)

Symbol	Bit range	R/W
FORCE_SHUTDOWN	25	RW
AUTO_SHUTDOWN_EN	24	RW
PWR_ON_DLY	23-16	RW
PWR_ON_SEQ_DLY	15-8	RW
ISO_ON_DLY	7-0	RW

9.1.14. PD_CP0_TD_CFG (0x402b0038)

Symbol	Bit range	R/W
FORCE_SHUTDOWN	25	RW
AUTO_SHUTDOWN_EN	24	RW
PWR_ON_DLY	23-16	RW
PWR_ON_SEQ_DLY	15-8	RW
ISO_ON_DLY	7-0	RW

9.1.15. PD_CP0_CEVA_0_CFG (0x402b003c)

Symbol	Bit range	R/W
FORCE_SHUTDOWN	25	RW
AUTO_SHUTDOWN_EN	24	RW
PWR_ON_DLY	23-16	RW
PWR_ON_SEQ_DLY	15-8	RW
ISO_ON_DLY	7-0	RW

9.1.16. PD_CP0_CEVA_1_CFG (0x402b0040)

Symbol	Bit range	R/W
FORCE_SHUTDOWN	25	RW
AUTO_SHUTDOWN_EN	24	RW
PWR_ON_DLY	23-16	RW
PWR_ON_SEQ_DLY	15-8	RW
ISO_ON_DLY	7-0	RW

9.1.17. PD_CP0_SYS_CFG (0x402b0044)

Symbol	Bit range	R/W	Description

9.1.18. PD_CP1_CA5_CFG (0x402b0048)

CP1 Cortex-A5 power down config

Symbol	Bit range	R/W
FORCE_SHUTDOWN	25	RW
AUTO_SHUTDOWN_EN	24	RW
PWR_ON_DLY	23-16	RW
PWR_ON_SEQ_DLY	15-8	RW
ISO_ON_DLY	7-0	RW

9.1.19. PD_CP1_LTE_P1_CFG (0x402b004c)

CP1 LTE P1 power down config

Symbol	Bit range	R/W
FORCE_SHUTDOWN	25	RW
AUTO_SHUTDOWN_EN	24	RW
PWR_ON_DLY	23-16	RW
PWR_ON_SEQ_DLY	15-8	RW
ISO_ON_DLY	7-0	RW

9.1.20. PD_CP1_LTE_P2_CFG (0x402b0050)

CP1 LTE P2 power down config

Symbol	Bit range	R/W
FORCE_SHUTDOWN	25	RW
AUTO_SHUTDOWN_EN	24	RW
PWR_ON_DLY	23-16	RW
PWR_ON_SEQ_DLY	15-8	RW
ISO_ON_DLY	7-0	RW

9.1.21. PD_CP1_CEVA_CFG (0x402b0054)

CP1 CEVA DSP power down config

Symbol	Bit range	R/W
FORCE_SHUTDOWN	25	RW
AUTO_SHUTDOWN_EN	24	RW
PWR_ON_DLY	23-16	RW
PWR_ON_SEQ_DLY	15-8	RW
ISO_ON_DLY	7-0	RW

9.1.22. PD_CP1_COMWRAP_CFG (0x402b0058)

Symbol	Bit range	R/W
FORCE_SHUTDOWN	25	RW
AUTO_SHUTDOWN_EN	24	RW
PWR_ON_DLY	23-16	RW
PWR_ON_SEQ_DLY	15-8	RW
ISO_ON_DLY	7-0	RW

9.1.23. PD_PUB_SYS_CFG (0x402b005c)

Symbol	Bit range	R/W
FORCE_SHUTDOWN	25	RW
AUTO_SHUTDOWN_EN	24	RW
PWR_ON_DLY	23-16	RW
PWR_ON_SEQ_DLY	15-8	RW
ISO_ON_DLY	7-0	RW

9.1.24. AP_WAKEUP_POR_CFG (0x402b0060)

Symbol	Bit range	R/W	Description
AP_WAKEUP_POR_N	0	RW

9.1.25. XTL_WAIT_CNT (0x402b0070)

Symbol	Bit range	R/W	Description
XTL1_WAIT_CNT	15-8	RW
XTL0_WAIT_CNT	7-0	RW

9.1.26. XTLBUF_WAIT_CNT (0x402b0074)

Symbol	Bit range	R/W	Description
XTLBUF1_WAIT_CNT	15-8	RW
XTLBUF0_WAIT_CNT	7-0	RW

9.1.27. PLL_WAIT_CNT1 (0x402b0078)

Symbol	Bit range	R/W
LTEPLL_WAIT_CNT	31-24	RW
TWPLL_WAIT_CNT	23-16	RW
DPLL_WAIT_CNT	15-8	RW
MPLL_WAIT_CNT	7-0	RW

9.1.28. PLL_WAIT_CNT2 (0x402b007c)

Symbol	Bit range	R/W	Description
LVDSDIS_PLL_WAIT_CNT	7-0	RW

9.1.29. XTL0_REL_CFG (0x402b0080)

Symbol	Bit range	R/W
XTL0_ARM7_SEL	5	RW
XTL0_VCP1_SEL	4	RW
XTL0_VCP0_SEL	3	RW
XTL0_CP1_SEL	2	RW
XTL0_CP0_SEL	1	RW
XTL0_AP_SEL	0	RW

9.1.30. XTL1_REL_CFG (0x402b0084)

Symbol	Bit range	R/W
XTL1_ARM7_SEL	5	RW
XTL1_VCP1_SEL	4	RW
XTL1_VCP0_SEL	3	RW
XTL1_CP1_SEL	2	RW
XTL1_CP0_SEL	1	RW
XTL1_AP_SEL	0	RW

9.1.31. XTLBUF0_REL_CFG (0x402b008c)

Symbol	Bit range	R/W
XTLBUF0_ARM7_SEL	5	RW
XTLBUF0_VCP1_SEL	4	RW
XTLBUF0_VCP0_SEL	3	RW
XTLBUF0_CP1_SEL	2	RW
XTLBUF0_CP0_SEL	1	RW
XTLBUF0_AP_SEL	0	RW

9.1.32. XTLBUF1_REL_CFG (0x402b0090)

Symbol	Bit range	R/W
XTLBUF1_ARM7_SEL	5	RW
XTLBUF1_VCP1_SEL	4	RW
XTLBUF1_VCP0_SEL	3	RW
XTLBUF1_CP1_SEL	2	RW
XTLBUF1_CP0_SEL	1	RW
XTLBUF1_AP_SEL	0	RW

9.1.33. MPLL_REL_CFG (0x402b0094)

Symbol	Bit range	R/W
MPLL_REF_SEL	8	RW
MPLL_ARM7_SEL	5	RW
MPLL_VCP1_SEL	4	RW
MPLL_VCP0_SEL	3	RW
MPLL_CP1_SEL	2	RW
MPLL_CP0_SEL	1	RW
MPLL_AP_SEL	0	RW

9.1.34. DPLL_REL_CFG (0x402b0098)

Symbol	Bit range	R/W
DPLL_REF_SEL	8	RW
DPLL_ARM7_SEL	5	RW
DPLL_VCP1_SEL	4	RW
DPLL_VCP0_SEL	3	RW
DPLL_CP1_SEL	2	RW
DPLL_CP0_SEL	1	RW
DPLL_AP_SEL	0	RW

9.1.35. LTEPLL_REL_CFG (0x402b009c)

Symbol	Bit range	R/W
LTEPLL_REF_SEL	8	RW
LTEPLL_ARM7_SEL	5	RW
LTEPLL_VCP1_SEL	4	RW
LTEPLL_VCP0_SEL	3	RW
LTEPLL_CP1_SEL	2	RW
LTEPLL_CP0_SEL	1	RW
LTEPLL_AP_SEL	0	RW

9.1.36. TWPLL_REL_CFG (0x402b00a0)

Symbol	Bit range	R/W
TWPLL_REF_SEL	8	RW
TWPLL_ARM7_SEL	5	RW
TWPLL_VCP1_SEL	4	RW
TWPLL_VCP0_SEL	3	RW
TWPLL_CP1_SEL	2	RW
TWPLL_CP0_SEL	1	RW
TWPLL_AP_SEL	0	RW

9.1.37. LVDSDIS_PLL_REL_CFG (0x402b00a4)

Symbol	Bit range	R/W
LVDSDIS_PLL_REF_SEL	8	RW
LVDSDIS_PLL_ARM7_SEL	5	RW
LVDSDIS_PLL_VCP1_SEL	4	RW
LVDSDIS_PLL_VCP0_SEL	3	RW
LVDSDIS_PLL_CP1_SEL	2	RW
LVDSDIS_PLL_CP0_SEL	1	RW
LVDSDIS_PLL_AP_SEL	0	RW

9.1.38. CP_SOFT_RST (0x402b00b0)

Communication processor soft reset

Symbol	Bit range	R/W
ARM7_SOFT_RST	8	RW
PUB_SOFT_RST	6	RW
AP_SOFT_RST	5	RW
GPU_SOFT_RST	4	RW
MM_SOFT_RST	3	RW
CODEC_SOFT_RST	2	RW
CP1_SOFT_RST	1	RW
CP0_SOFT_RST	0	RW

9.1.39. CP_SLP_STATUS_DBG0 (0x402b00b4)

Symbol	Bit range	R/W	Description
CP1_DEEP_SLP_DBG	31-16	R?
CP0_DEEP_SLP_DBG	15-0	R?

9.1.40. PWR_STATUS0_DBG (0x402b00bc)

Symbol	Bit range	R/W
PD_MM_TOP_STATE	31-28	R?
PD_GPU_TOP_STATE	27-24	R?
PD_AP_SYS_STATE	23-20	R?
PD_CA7_C3_STATE	19-16	R?
PD_CA7_C2_STATE	15-12	R?
PD_CA7_C1_STATE	11-8	R?
PD_CA7_C0_STATE	7-4	R?
PD_CA7_TOP_STATE	3-0	R?

9.1.41. PWR_STATUS1_DBG (0x402b00c0)

Symbol	Bit range	R/W
PD_CP0_CEVA_1_STATE	31-28	R?
PD_CP0_CEVA_0_STATE	27-24	R?
PD_CP0_GSM_0_STATE	23-20	R?
PD_CP0_GSM_1_STATE	19-16	R?
PD_CP0_HU3GE_STATE	15-12	R?
PD_CP0_ARM9_1_STATE	11-8	R?
PD_CP0_ARM9_0_STATE	7-4	R?
PD_CP0_TD_STATE	3-0	R?

9.1.42. PWR_STATUS2_DBG (0x402b00c4)

Symbol	Bit range	R/W
PD_PUB_SYS_STATE	27-24	R?
PD_CP1_COMWRAP_STATE	23-20	R?
PD_CP1_LTE_P2_STATE	19-16	R?
PD_CP1_LTE_P1_STATE	15-12	R?
PD_CP1_CEVA_STATE	11-8	R?
PD_CP1_CA5_STATE	7-4	R?

9.1.43. SLEEP_CTRL (0x402b00cc)

Symbol	Bit range	R/W
VCP1_FORCE_LIGHT_SLEEP	28	RW
VCP0_FORCE_LIGHT_SLEEP	27	RW
CP1_FORCE_LIGHT_SLEEP	26	RW
CP0_FORCE_LIGHT_SLEEP	25	RW
AP_FORCE_LIGHT_SLEEP	24	RW
ARM7_FORCE_DEEP_SLEEP	21	RW
VCP1_FORCE_DEEP_SLEEP	20	RW
VCP0_FORCE_DEEP_SLEEP	19	RW
CP1_FORCE_DEEP_SLEEP	18	RW
CP0_FORCE_DEEP_SLEEP	17	RW
AP_FORCE_DEEP_SLEEP	16	RW
VCP1_LIGHT_SLEEP	12	RW
VCP0_LIGHT_SLEEP	11	RW
CP1_LIGHT_SLEEP	10	RW
CP0_LIGHT_SLEEP	9	RW
AP_LIGHT_SLEEP	8	RW
VCP1_DEEP_SLEEP	4	RW
VCP0_DEEP_SLEEP	3	RW
CP1_DEEP_SLEEP	2	RW
CP0_DEEP_SLEEP	1	RW
AP_DEEP_SLEEP	0	RW

9.1.44. DDR_SLEEP_CTRL (0x402b00d0)

Symbol	Bit range	R/W
BUSY_TRANSFER_HWDATA_SEL	16	RW
DDR_PUBL_APB_SOFT_RST	12	RW
DDR_UMCTL_APB_SOFT_RST	11	RW
DDR_PUBL_SOFT_RST	10	RW
DDR_PHY_SOFT_RST	8	RW
DDR_PHY_AUTO_GATE_EN	6	RW
DDR_PUBL_AUTO_GATE_EN	5	RW
DDR_UMCTL_AUTO_GATE_EN	4	RW
DDR_PHY_EB	2	RW
DDR_UMCTL_EB	1	RW
DDR_PUBL_EB	0	RW

9.1.45. SLEEP_STATUS (0x402b00d4)

Symbol	Bit range	R/W
ARM7_SLP_STATUS	23-20	R?
VCP1_SLP_STATUS	19-16	R?
VCP0_SLP_STATUS	15-12	R?
CP1_SLP_STATUS	11-8	R?
CP0_SLP_STATUS	7-4	R?
AP_SLP_STATUS	3-0	R?

9.1.46. CA7_TOP_CFG (0x402b00e4)

Symbol	Bit range	R/W	Description
CA7_L2RSTDISABLE	0	RW

9.1.47. CA7_C0_CFG (0x402b00e8)

Symbol	Bit range	R/W	Description
CA7_VINITHI_C0	0	RW

9.1.48. CA7_C1_CFG (0x402b00ec)

Symbol	Bit range	R/W	Description
CA7_VINITHI_C1	0	RW

9.1.49. CA7_C2_CFG (0x402b00f0)

Symbol	Bit range	R/W	Description
CA7_VINITHI_C2	0	RW

9.1.50. CA7_C3_CFG (0x402b00f4)

Symbol	Bit range	R/W	Description
CA7_VINITHI_C3	0	RW

9.1.51. DDR_CHN_SLEEP_CTRL0 (0x402b00f8)

Symbol	Bit range	R/W
DDR_CTRL_AXI_LP_EN	31	RW
DDR_CTRL_CGM_SEL	30	RW
DDR_CHN9_AXI_LP_EN	25	RW
DDR_CHN8_AXI_LP_EN	24	RW
DDR_CHN7_AXI_LP_EN	23	RW
DDR_CHN6_AXI_LP_EN	22	RW
DDR_CHN5_AXI_LP_EN	21	RW
DDR_CHN4_AXI_LP_EN	20	RW
DDR_CHN3_AXI_LP_EN	19	RW
DDR_CHN2_AXI_LP_EN	18	RW
DDR_CHN1_AXI_LP_EN	17	RW
DDR_CHN0_AXI_LP_EN	16	RW
DDR_CHN9_CGM_SEL	9	RW
DDR_CHN8_CGM_SEL	8	RW
DDR_CHN7_CGM_SEL	7	RW
DDR_CHN6_CGM_SEL	6	RW
DDR_CHN5_CGM_SEL	5	RW
DDR_CHN4_CGM_SEL	4	RW
DDR_CHN3_CGM_SEL	3	RW
DDR_CHN2_CGM_SEL	2	RW
DDR_CHN1_CGM_SEL	1	RW
DDR_CHN0_CGM_SEL	0	RW

9.1.52. DDR_CHN_SLEEP_CTRL1 (0x402b00fc)

Symbol	Bit range	R/W
DDR_CHN9_AXI_STOP_SEL	9	RW
DDR_CHN8_AXI_STOP_SEL	8	RW
DDR_CHN7_AXI_STOP_SEL	7	RW
DDR_CHN6_AXI_STOP_SEL	6	RW
DDR_CHN5_AXI_STOP_SEL	5	RW
DDR_CHN4_AXI_STOP_SEL	4	RW
DDR_CHN3_AXI_STOP_SEL	3	RW
DDR_CHN2_AXI_STOP_SEL	2	RW
DDR_CHN1_AXI_STOP_SEL	1	RW
DDR_CHN0_AXI_STOP_SEL	0	RW

9.1.53. DDR_OP_MODE_CFG (0x402b012c)

Symbol	Bit range	R/W
DDR_OPERATE_MODE_BUSY	28	R
DDR_PUBL_RET_EN	27	RW
DDR_PHY_ISO_RST_EN	26	RW
DDR_UMCTL_RET_EN	25	RW
DDR_PHY_AUTO_RET_EN	24	RW
DDR_OPERATE_MODE_CNT_LMT	23-16	RW
DDR_OPERATE_MODE	10-8	RW
DDR_OPERATE_MODE_IDLE	2-0	RW

9.1.54. DDR_PHY_RET_CFG (0x402b0130)

Symbol	Bit range	R/W	Description
DDR_UMCTL_SOFT_RST	16	RW
DDR_PHY_CKE_RET_EN	0	RW

9.1.55. 26M_SEL_CFG (0x402b0134)

Symbol	Bit range	R/W
AON_RC_4M_SEL	8	RW
GGE_26M_SEL	6	RW
PUB_26M_SEL	5	RW
AON_26M_SEL	4	RW
CP1_26M_SEL	2	RW
CP0_26M_SEL	1	RW
AP_26M_SEL	0	RW

9.1.56. BISR_DONE_STATUS (0x402b0138)

Symbol	Bit range	R/W
PD_CP1_COMWRAP_BISR_DONE	21	R
PD_CP1_LTE_P2_BISR_DONE	20	R
PD_CP1_LTE_P1_BISR_DONE	19	R
PD_CP1_CEVA_BISR_DONE	18	R
PD_CP1_CA5_BISR_DONE	17	R
PD_CODEC_TOP_BISR_DONE	16	R
PD_CP0_HU3GE_BISR_DONE	15	R
PD_CP0_TD_BISR_DONE	14	R
PD_CP0_GSM_1_BISR_DONE	13	R
PD_CP0_GSM_0_BISR_DONE	12	R
PD_CP0_CEVA_1_BISR_DONE	11	R
PD_CP0_CEVA_0_BISR_DONE	10	R
PD_CP0_ARM9_1_BISR_DONE	9	R
PD_CP0_ARM9_0_BISR_DONE	8	R
PD_MM_TOP_BISR_DONE	7	R
PD_GPU_TOP_BISR_DONE	6	R
PD_AP_SYS_BISR_DONE	5	R
PD_CA7_TOP_BISR_DONE	4	R
PD_CA7_C3_BISR_DONE	3	R
PD_CA7_C2_BISR_DONE	2	R
PD_CA7_C1_BISR_DONE	1	R
PD_CA7_C0_BISR_DONE	0	R

9.1.57. BISR_BUSY_STATUS (0x402b013c)

Symbol	Bit range	R/W
PD_CP1_COMWRAP_BISR_BUSY	21	R
PD_CP1_LTE_P2_BISR_BUSY	20	R
PD_CP1_LTE_P1_BISR_BUSY	19	R
PD_CP1_CEVA_BISR_BUSY	18	R
PD_CP1_CA5_BISR_BUSY	17	R
PD_CODEC_TOP_BISR_BUSY	16	R
PD_CP0_HU3GE_BISR_BUSY	15	R
PD_CP0_TD_BISR_BUSY	14	R
PD_CP0_GSM_1_BISR_BUSY	13	R
PD_CP0_GSM_0_BISR_BUSY	12	R
PD_CP0_CEVA_1_BISR_BUSY	11	R
PD_CP0_CEVA_0_BISR_BUSY	10	R
PD_CP0_ARM9_1_BISR_BUSY	9	R
PD_CP0_ARM9_0_BISR_BUSY	8	R
PD_MM_TOP_BISR_BUSY	7	R
PD_GPU_TOP_BISR_BUSY	6	R
PD_AP_SYS_BISR_BUSY	5	R
PD_CA7_TOP_BISR_BUSY	4	R
PD_CA7_C3_BISR_BUSY	3	R
PD_CA7_C2_BISR_BUSY	2	R
PD_CA7_C1_BISR_BUSY	1	R
PD_CA7_C0_BISR_BUSY	0	R

9.1.58. BISR_BYP_CFG (0x402b0140)

Symbol	Bit range	R/W
PD_CP1_COMWRAP_BISR_FORCE_BYP	21	RW
PD_CP1_LTE_P2_BISR_FORCE_BYP	20	RW
PD_CP1_LTE_P1_BISR_FORCE_BYP	19	RW
PD_CP1_CEVA_BISR_FORCE_BYP	18	RW
PD_CP1_CA5_BISR_FORCE_BYP	17	RW
PD_CODEC_TOP_BISR_FORCE_BYP	16	RW
PD_CP0_HU3GE_BISR_FORCE_BYP	15	RW
PD_CP0_TD_BISR_FORCE_BYP	14	RW
PD_CP0_GSM_1_BISR_FORCE_BYP	13	RW
PD_CP0_GSM_0_BISR_FORCE_BYP	12	RW
PD_CP0_CEVA_1_BISR_FORCE_BYP	11	RW
PD_CP0_CEVA_0_BISR_FORCE_BYP	10	RW
PD_CP0_ARM9_1_BISR_FORCE_BYP	9	RW
PD_CP0_ARM9_0_BISR_FORCE_BYP	8	RW
PD_MM_TOP_BISR_FORCE_BYP	7	RW
PD_GPU_TOP_BISR_FORCE_BYP	6	RW
PD_AP_SYS_BISR_FORCE_BYP	5	RW
PD_CA7_TOP_BISR_FORCE_BYP	4	RW
PD_CA7_C3_BISR_FORCE_BYP	3	RW
PD_CA7_C2_BISR_FORCE_BYP	2	RW
PD_CA7_C1_BISR_FORCE_BYP	1	RW
PD_CA7_C0_BISR_FORCE_BYP	0	RW

9.1.59. BISR_EN_CFG (0x402b0144)

Symbol	Bit range	R/W
PD_CP1_COMWRAP_BISR_FORCE_EN	21	RW
PD_CP1_LTE_P2_BISR_FORCE_EN	20	RW
PD_CP1_LTE_P1_BISR_FORCE_EN	19	RW
PD_CP1_CEVA_BISR_FORCE_EN	18	RW
PD_CP1_CA5_BISR_FORCE_EN	17	RW
PD_CODEC_TOP_BISR_FORCE_EN	16	RW
PD_CP0_HU3GE_BISR_FORCE_EN	15	RW
PD_CP0_TD_BISR_FORCE_EN	14	RW
PD_CP0_GSM_1_BISR_FORCE_EN	13	RW
PD_CP0_GSM_0_BISR_FORCE_EN	12	RW
PD_CP0_CEVA_1_BISR_FORCE_EN	11	RW
PD_CP0_CEVA_0_BISR_FORCE_EN	10	RW
PD_CP0_ARM9_1_BISR_FORCE_EN	9	RW
PD_CP0_ARM9_0_BISR_FORCE_EN	8	RW
PD_MM_TOP_BISR_FORCE_EN	7	RW
PD_GPU_TOP_BISR_FORCE_EN	6	RW
PD_AP_SYS_BISR_FORCE_EN	5	RW
PD_CA7_TOP_BISR_FORCE_EN	4	RW
PD_CA7_C3_BISR_FORCE_EN	3	RW
PD_CA7_C2_BISR_FORCE_EN	2	RW
PD_CA7_C1_BISR_FORCE_EN	1	RW
PD_CA7_C0_BISR_FORCE_EN	0	RW

9.1.60. CGM_AUTO_GATE_SEL_CFG0 (0x402b0148)

Symbol	Bit range	R/W	Description
CGM_AUTO_GATE_SEL_CFG0	31-0	RW

9.1.61. CGM_AUTO_GATE_SEL_CFG1 (0x402b014c)

Symbol	Bit range	R/W	Description
CGM_AUTO_GATE_SEL_CFG1	31-0	RW

9.1.62. CGM_AUTO_GATE_SEL_CFG2 (0x402b0150)

Symbol	Bit range	R/W	Description
CGM_AUTO_GATE_SEL_CFG2	31-0	RW

9.1.63. CGM_AUTO_GATE_SEL_CFG3 (0x402b0154)

Symbol	Bit range	R/W	Description
CGM_AUTO_GATE_SEL_CFG3	31-0	RW

9.1.64. CGM_FORCE_EN_CFG0 (0x402b0158)

Symbol	Bit range	R/W	Description
CGM_FORCE_EN_CFG0	31-0	RW

9.1.65. CGM_FORCE_EN_CFG1 (0x402b015c)

Symbol	Bit range	R/W	Description
CGM_FORCE_EN_CFG1	31-0	RW

9.1.66. CGM_FORCE_EN_CFG2 (0x402b0160)

Symbol	Bit range	R/W	Description
CGM_FORCE_EN_CFG2	31-0	RW

9.1.67. CGM_FORCE_EN_CFG3 (0x402b0164)

Symbol	Bit range	R/W	Description
CGM_FORCE_EN_CFG3	31-0	RW

9.1.68. SLEEP_XTLON_CTRL (0x402b0168)

Symbol	Bit range	R/W
ARM7_SLEEP_XTL_ON	5	RW
VCP1_SLEEP_XTL_ON	4	RW
VCP0_SLEEP_XTL_ON	3	RW
CP1_SLEEP_XTL_ON	2	RW
CP0_SLEEP_XTL_ON	1	RW
AP_SLEEP_XTL_ON	0	RW

9.1.69. MEM_SLP_CFG (0x402b016c)

Symbol	Bit range	R/W	Description
MEM_SLP_CFG	31-0	RW

9.1.70. MEM_SD_CFG (0x402b0170)

Symbol	Bit range	R/W	Description
MEM_SD_CFG	31-0	RW

9.1.71. CA7_CORE_PU_LOCK (0x402b0174)

Symbol	Bit range	R/W
CA7_C3_GIC_WAKEUP_EN	11	RW
CA7_C2_GIC_WAKEUP_EN	10	RW
CA7_C1_GIC_WAKEUP_EN	9	RW
CA7_C0_GIC_WAKEUP_EN	8	RW
CA7_C3_PU_LOCK	3	RW
CA7_C2_PU_LOCK	2	RW
CA7_C1_PU_LOCK	1	RW
CA7_C0_PU_LOCK	0	RW

9.1.72. ARM7_HOLD_CGM_EN (0x402b0178)

Symbol	Bit range	R/W
PD_CP1_CEVA_CGM_HOLD_EN	10	RW
PD_CP1_CA5_CGM_HOLD_EN	9	RW
PD_CP0_CEVA_1_CGM_HOLD_EN	8	RW
PD_CP0_CEVA_0_CGM_HOLD_EN	7	RW
PD_CP0_ARM9_1_CGM_HOLD_EN	6	RW
PD_CP0_ARM9_0_CGM_HOLD_EN	5	RW
PD_CA7_TOP_CMG_HOLD_EN	4	RW
PD_CA7_C3_CMG_HOLD_EN	3	RW
PD_CA7_C2_CMG_HOLD_EN	2	RW
PD_CA7_C1_CMG_HOLD_EN	1	RW
PD_CA7_C0_CMG_HOLD_EN	0	RW

9.1.73. PWR_CNT_WAIT_CFG0 (0x402b017c)

Symbol	Bit range	R/W
VCP0_PWR_WAIT_CNT	31-24	RW
CP1_PWR_WAIT_CNT	23-16	RW
CP0_PWR_WAIT_CNT	15-8	RW
AP_PWR_WAIT_CNT	7-0	RW

9.1.74. PWR_CNT_WAIT_CFG1 (0x402b0180)

Symbol	Bit range	R/W	Description
ARM7_PWR_WAIT_CNT	15-8	RW
VCP1_PWR_WAIT_CNT	7-0	RW

9.1.75. RC0_REL_CFG (0x402b0184)

Symbol	Bit range	R/W
RC0_ARM7_SEL	5	RW
RC0_VCP1_SEL	4	RW
RC0_VCP0_SEL	3	RW
RC0_CP1_SEL	2	RW
RC0_CP0_SEL	1	RW
RC0_AP_SEL	0	RW

9.1.76. RC1_REL_CFG (0x402b0188)

Symbol	Bit range	R/W
RC1_ARM7_SEL	5	RW
RC1_VCP1_SEL	4	RW
RC1_VCP0_SEL	3	RW
RC1_CP1_SEL	2	RW
RC1_CP0_SEL	1	RW
RC1_AP_SEL	0	RW

9.1.77. RC_CNT_WAIT_CFG (0x402b018c)

Symbol	Bit range	R/W	Description
RC1_WAIT_CNT	15-8	RW
RC0_WAIT_CNT	7-0	RW

9.1.78. MEM_AUTO_SLP_CFG (0x402b0190)

Symbol	Bit range	R/W	Description
MEM_AUTO_SLP_EN	31-0	RW

9.1.79. MEM_AUTO_SD_CFG (0x402b0194)

Symbol	Bit range	R/W	Description
MEM_AUTO_SD_EN	31-0	RW

9.1.80. CP0_PD_SHUTDOWN_CFG (0x402b0198)

Symbol	Bit range	R/W
PD_CP0_HU3GE_VCP1_SEL	20	RW
PD_CP0_TD_VCP1_SEL	19	RW
PD_CP0_GSM_0_VCP1_SEL	18	RW
PD_CP0_CEVA_0_VCP1_SEL	17	RW
PD_CP0_ARM9_1_VCP1_SEL	16	RW
PD_CP0_ARM9_0_VCP0_SEL	8	RW
PD_CP0_HU3GE_CP0_SEL	5	RW
PD_CP0_TD_CP0_SEL	4	RW
PD_CP0_GSM_0_CP0_SEL	3	RW
PD_CP0_CEVA_0_CP0_SEL	2	RW
PD_CP0_ARM9_1_CP0_SEL	1	RW
PD_CP0_ARM9_0_CP0_SEL	0	RW

9.1.81. CP1_PD_SHUTDOWN_CFG (0x402b019c)

Symbol	Bit range	R/W
PD_CP1_COMWRAP_VCP1_SEL	20	RW
PD_CP1_CEVA_VCP1_SEL	19	RW
PD_CP1_LTE_P2_VCP1_SEL	18	RW
PD_CP1_LTE_P1_VCP1_SEL	17	RW
PD_CP1_CA5_VCP1_SEL	16	RW
PD_CP1_COMWRAP_CP1_SEL	4	RW
PD_CP1_CEVA_CP1_SEL	3	RW
PD_CP1_LTE_P2_CP1_SEL	2	RW
PD_CP1_LTE_P1_CP1_SEL	1	RW
PD_CP1_CA5_CP1_SEL	0	RW

9.1.82. WAKEUP_LOCK_EN (0x402b01a0)

Symbol	Bit range	R/W
VCP1_SYS_WAKEUP_LOCK_EN	26	RW
VCP0_SYS_WAKEUP_LOCK_EN	25	RW
CP1_SYS_WAKEUP_LOCK_EN	24	RW
CP0_SYS_WAKEUP_LOCK_EN	23	RW
AP_SYS_WAKEUP_LOCK_EN	22	RW
PD_PUB_SYS_WAKEUP_LOCK_EN	21	RW
PD_CP1_COMWRAP_WAKEUP_LOCK_EN	20	RW
PD_CP1_CEVA_WAKEUP_LOCK_EN	19	RW
PD_CP1_LTE_P2_WAKEUP_LOCK_EN	18	RW
PD_CP1_LTE_P1_WAKEUP_LOCK_EN	17	RW
PD_CP1_CA5_WAKEUP_LOCK_EN	16	RW
PD_CP0_CEVA_1_WAKEUP_LOCK_EN	15	RW
PD_CP0_CEVA_0_WAKEUP_LOCK_EN	14	RW
PD_CP0_TD_WAKEUP_LOCK_EN	13	RW
PD_CP0_GSM_1_WAKEUP_LOCK_EN	12	RW
PD_CP0_GSM_0_WAKEUP_LOCK_EN	11	RW
PD_CP0_HU3GE_WAKEUP_LOCK_EN	10	RW
PD_CP0_ARM9_1_WAKEUP_LOCK_EN	9	RW
PD_CP0_ARM9_0_WAKEUP_LOCK_EN	8	RW
PD_MM_TOP_WAKEUP_LOCK_EN	7	RW
PD_GPU_TOP_WAKEUP_LOCK_EN	6	RW
PD_AP_SYS_WAKEUP_LOCK_EN	5	RW
PD_CA7_TOP_WAKEUP_LOCK_EN	4	RW
PD_CA7_C3_WAKEUP_LOCK_EN	3	RW
PD_CA7_C2_WAKEUP_LOCK_EN	2	RW
PD_CA7_C1_WAKEUP_LOCK_EN	1	RW
PD_CA7_C0_WAKEUP_LOCK_EN	0	RW

9.1.83. PD_CODEC_TOP_CFG (0x402b01a4)

Symbol	Bit range	R/W
PD_CODEC_TOP_FORCE_SHUTDOWN	25	RW
PD_CODEC_TOP_AUTO_SHUTDOWN_EN	24	RW
PD_CODEC_TOP_PWR_ON_DLY	23-16	RW
PD_CODEC_TOP_PWR_ON_SEQ_DLY	15-8	RW
PD_CODEC_TOP_ISO_ON_DLY	7-0	RW

9.1.84. PD_CA7_C0_SHUTDOWN_MARK_STATUS (0x402b3000)

Symbol	Bit range	R/W	Description
PD_CA7_C0_SHUTDOWN_MARK	3-0	R

9.1.85. PD_CA7_C1_SHUTDOWN_MARK_STATUS (0x402b3004)

Symbol	Bit range	R/W	Description
PD_CA7_C1_SHUTDOWN_MARK	3-0	R

9.1.86. PD_CA7_C2_SHUTDOWN_MARK_STATUS (0x402b3008)

Symbol	Bit range	R/W	Description
PD_CA7_C2_SHUTDOWN_MARK	3-0	R

9.1.87. PD_CA7_C3_SHUTDOWN_MARK_STATUS (0x402b300c)

Symbol	Bit range	R/W	Description
PD_CA7_C3_SHUTDOWN_MARK	3-0	R

9.1.88. PD_CA7_TOP_SHUTDOWN_MARK_STATUS (0x402b3010)

Symbol	Bit range	R/W	Description
PD_CA7_TOP_SHUTDOWN_MARK	3-0	R

9.1.89. PD_AP_SYS_SHUTDOWN_MARK_STATUS (0x402b3014)

Symbol	Bit range	R/W	Description
PD_AP_SYS_SHUTDOWN_MARK	3-0	R

9.1.90. PD_GPU_TOP_SHUTDOWN_MARK_STATUS (0x402b3018)

Symbol	Bit range	R/W	Description
PD_GPU_TOP_SHUTDOWN_MARK	3-0	R

9.1.91. PD_MM_TOP_SHUTDOWN_MARK_STATUS (0x402b301c)

Symbol	Bit range	R/W	Description
PD_MM_TOP_SHUTDOWN_MARK	3-0	R

9.1.92. PD_CP0_ARM9_0_SHUTDOWN_MARK_STATUS (0x402b3020)

Symbol	Bit range	R/W	Description
PD_CP0_ARM9_0_SHUTDOWN_MARK	3-0	R

9.1.93. PD_CP0_ARM9_1_SHUTDOWN_MARK_STATUS (0x402b3024)

Symbol	Bit range	R/W	Description
PD_CP0_ARM9_1_SHUTDOWN_MARK	3-0	R

9.1.94. PD_CP0_CEVA_0_SHUTDOWN_MARK_STATUS (0x402b3028)

Symbol	Bit range	R/W	Description
PD_CP0_CEVA_0_SHUTDOWN_MARK	3-0	R

9.1.95. PD_CP0_CEVA_1_SHUTDOWN_MARK_STATUS (0x402b302c)

Symbol	Bit range	R/W	Description
PD_CP0_CEVA_1_SHUTDOWN_MARK	3-0	R

9.1.96. PD_CP0_GSM_0_SHUTDOWN_MARK_STATUS (0x402b3030)

Symbol	Bit range	R/W	Description
PD_CP0_GSM_0_SHUTDOWN_MARK	3-0	R

9.1.97. PD_CP0_GSM_1_SHUTDOWN_MARK_STATUS (0x402b3034)

Symbol	Bit range	R/W	Description
PD_CP0_GSM_1_SHUTDOWN_MARK	3-0	R

9.1.98. PD_CP0_TD_SHUTDOWN_MARK_STATUS (0x402b3038)

Symbol	Bit range	R/W	Description
PD_CP0_TD_SHUTDOWN_MARK	3-0	R

9.1.99. PD_CP0_HU3GE_SHUTDOWN_MARK_STATUS (0x402b303c)

Symbol	Bit range	R/W	Description
PD_CP0_HU3GE_SHUTDOWN_MARK	3-0	R

9.1.100. PD_CP1_CEVA_SHUTDOWN_MARK_STATUS (0x402b3040)

Symbol	Bit range	R/W	Description
PD_CP1_CA5_SHUTDOWN_MARK	3-0	R

9.1.101. PD_CP1_CEVA_SHUTDOWN_MARK_STATUS (0x402b3044)

Symbol	Bit range	R/W	Description
PD_CP1_CEVA_SHUTDOWN_MARK	3-0	R

9.1.102. PD_CP1_LTE_P1_SHUTDOWN_MARK_STATUS (0x402b3048)

Symbol	Bit range	R/W	Description
PD_CP1_LTE_P1_SHUTDOWN_MARK	3-0	R

9.1.103. PD_CP1_LTE_P2_SHUTDOWN_MARK_STATUS (0x402b304c)

Symbol	Bit range	R/W	Description
PD_CP1_LTE_P2_SHUTDOWN_MARK	3-0	R

9.1.104. PD_CP1_COMWRAP_SHUTDOWN_MARK_STATUS (0x402b3050)

Symbol	Bit range	R/W	Description
PD_CP1_COMWRAP_SHUTDOWN_MARK	3-0	R

9.1.105. PD_PUB_SYS_SHUTDOWN_MARK_STATUS (0x402b3054)

Symbol	Bit range	R/W	Description
PD_PUB_SYS_SHUTDOWN_MARK	3-0	R

9.1.106. PD_CODEC_TOP_SHUTDOWN_MARK_STATUS (0x402b3058)

Symbol	Bit range	R/W	Description
PD_CODEC_TOP_SHUTDOWN_MARK	3-0	R

10. AON APB control

Base address
0x402e0000

10.1. Registers

Symbol	Offset	Description
APB_EB0	0x0000	APB enable bits 0
APB_EB1	0x0004	APB enable bits 1
APB_RST0	0x0008	APB reset 0
APB_RST1	0x000c	APB reset 1
APB_RTC_EB	0x0010	APB RTC enable bits 0
REC_26MHZ_BUF_CFG	0x0014
SINDRV_CTRL	0x0018
ADA_SEL_CTRL	0x001c
VBC_CTRL	0x0020
PWR_CTRL	0x0024
TS_CFG	0x0028
BOOT_MODE	0x002c
BB_BG_CTRL	0x0030
CP_ARM_JTAG_CTRL	0x0034
PLL_SOFT_CNT_DONE	0x0038
DCXO_LC_REG0	0x003c
DCXO_LC_REG1	0x0040
MPLL_CFG1	0x0044
MPLL_CFG2	0x0048
DPLL_CFG1	0x004c
DPLL_CFG2	0x0050
TWPLL_CFG1	0x0054
TWPLL_CFG2	0x0058
LTEPLL_CFG1	0x005c
LTEPLL_CFG2	0x0060
LVDSDISPLL_CFG1	0x0064
LVDSDISPLL_CFG2	0x0068
AON_REG_PROT	0x006c	Protect register (big endian)
LDSP_BOOT_EN	0x0070	DSP boot enable
LDSP_BOOT_VEC	0x0074	DSP boot vector
LDSP_RST	0x0078	DSP reset
LDSP_MTX_CTRL1	0x007c
LDSP_MTX_CTRL2	0x0080
LDSP_MTX_CTRL3	0x0084
AON_CGM_CFG	0x0088
LACC_MTX_CTRL	0x008c
CORTEX_MTX_CTRL1	0x0090
CORTEX_MTX_CTRL2	0x0094
CORTEX_MTX_CTRL3	0x0098
CA5_TCLK_DLY_LEN	0x009c
?	0x00b4	Mystery register used by ROM code.
AON_CHIP_ID_H	0x00f8
AON_CHIP_ID_L	0x00fc
CCIR_RCVR_CFG	0x0100
PLL_BG_CFG	0x0108
LVDSDIS_SEL	0x010c
DJTAG_MUX_SEL	0x0110
ARM7_SYS_SOFT_RST	0x0114
CP1_CP0_ADDR_MSB	0x0118
AON_DMA_INT_EN	0x011c
EMC_AUTO_GATE_EN	0x0120
ARM7_CFG_BUS	0x0124
RTC4M_0_CFG	0x0128
RTC4M_1_CFG	0x012c
APB_RST2	0x0130
AP_WPROT_EN1	0x3004
CP0_WPROT_EN1	0x3008
CP1_WPROT_EN1	0x300c
IO_DLY_CTRL	0x3014
AP_WPROT_EN0	0x3018
CP0_WPROT_EN0	0x3020
CP1_WPROT_EN0	0x3024
PMU_RST_MONITOR	0x302c
THM_RST_MONITOR	0x3030
AP_RST_MONITOR	0x3034
CA7_RST_MONITOR	0x3038
BOND_OPT0	0x303c
BOND_OPT1	0x3040
RES_REG0	0x3044
RES_REG1	0x3048
AON_QOS_CFG	0x304c
BB_LDO_CAL_START	0x3050
AON_MTX_PROT_CFG	0x3058
LVDS_CFG	0x3060
PLL_LOCK_OUT_SEL	0x3064
RTC4M_RC_VAL	0x3068
AON_APB_RSV	0x30f0

10.1.1. APB_EB0 (0x402e0000)

Symbol	Bit range	R/W
I2C_EB	31	RW
CA7_DAP_EB	30	RW
CA7_TS1_EB	29	RW
CA7_TS0_EB	28	RW
GPU_EB	27	RW
AON_CKG_EB	26	RW
MM_EB	25	RW
AP_WDG_EB	24	RW
MSPI_EB	23	RW
SPLK_EB	22	RW
IPI_EB	21	RW
PIN_EB	20	RW
VBC_EB	19	RW
AUD_EB	18	RW
AUDIF_EB	17	RW
ADI_EB	16	RW
INTC_EB	15	RW
EIC_EB	14	RW
EFUSE_EB	13	RW
AP_TMR0_EB	12	RW
AON_TMR_EB	11	RW
AP_SYST_EB	10	RW
AON_SYST_EB	9	RW
KPD_EB	8	RW
PWM3_EB	7	RW
PWM2_EB	6	RW
PWM1_EB	5	RW
PWM0_EB	4	RW
GPIO_EB	3	RW
TPC_EB	2	RW
FM_EB	1	RW
ADC_EB	0	RW

10.1.2. APB_EB1 (0x402e0004)

Symbol	Bit range	R/W
CODEC_EB	28	RW
ORP_JTAG_EB	27	RW
CA5_TS0_EB	26	RW
DEF_EB	25	RW
LVDS_PLL_DIV_EB	24	RW
ARM7_JTAG_EB	23	RW
AON_DMA_EB	22	RW
MBOX_EB	21	RW
DJTAG_EB	20	RW
RTC4M1_CAL_EB	19	RW
RTC4M0_CAL_EB	18	RW
MDAR_EB	17	RW
LVDS_TCXO_EB	16	RW
LVDS_TRX_EB	15	RW
CA5_DAP_EB	14	RW
GSP_EMC_EB	13	RW
ZIP_EMC_EB	12	RW
DISP_EMC_EB	11	RW
AP_TMR2_EB	10	RW
AP_TMR1_EB	9	RW
CA7_WDG_EB	8	RW
	7	RW
AVS_EB	6	RW
PROBE_EB	5	RW
AUX2_EB	4	RW
AUX1_EB	3	RW
AUX0_EB	2	RW
THM_EB	1	RW
PMU_EB	0	RW

10.1.3. APB_RST0 (0x402e0008)

Symbol	Bit range	R/W
CA5_TS0_SOFT_RST	31	RW
I2C_SOFT_RST	30	RW
CA7_TS1_SOFT_RST	29	RW
CA7_TS0_SOFT_RST	28	RW
DAP_MTX_SOFT_RST	27	RW
MSPI1_SOFT_RST	26	RW
MSPI0_SOFT_RST	25	RW
SPLK_SOFT_RST	24	RW
IPI_SOFT_RST	23	RW
AON_CKG_SOFT_RST	22	RW
PIN_SOFT_RST	21	RW
VBC_SOFT_RST	20	RW
AUD_SOFT_RST	19	RW
AUDIF_SOFT_RST	18	RW
ADI_SOFT_RST	17	RW
INTC_SOFT_RST	16	RW
EIC_SOFT_RST	15	RW
EFUSE_SOFT_RST	14	RW
AP_WDG_SOFT_RST	13	RW
AP_TMR0_SOFT_RST	12	RW
AON_TMR_SOFT_RST	11	RW
AP_SYST_SOFT_RST	10	RW
AON_SYST_SOFT_RST	9	RW
KPD_SOFT_RST	8	RW
PWM3_SOFT_RST	7	RW
PWM2_SOFT_RST	6	RW
PWM1_SOFT_RST	5	RW
PWM0_SOFT_RST	4	RW
GPIO_SOFT_RST	3	RW
TPC_SOFT_RST	2	RW
FM_SOFT_RST	1	RW
ADC_SOFT_RST	0	RW

10.1.4. APB_RST1 (0x402e000c)

Symbol	Bit range	R/W
RTC4M_ANA_SOFT_RST	31	RW
DEF_SLV_INT_SOFT_RST	30	RW
DEF_SOFT_RST	29	RW
ADC3_SOFT_RST	28	RW
ADC2_SOFT_RST	27	RW
ADC1_SOFT_RST	26	RW
MBOX_SOFT_RST	25	RW
xxx_SOFT_RST	24	RW
RTC4M1_CAL_SOFT_RST	23	RW
RTC4M0_CAL_SOFT_RST	22	RW
LDSP_SYS_SOFT_RST	21	RW
LCP_SYS_SOFT_RST	20	RW
DAC3_SOFT_RST	19	RW
DAC2_SOFT_RST	18	RW
DAC1_SOFT_RST	17	RW
ADC3_CAL_SOFT_RST	16	RW
ADC2_CAL_SOFT_RST	15	RW
ADC1_CAL_SOFT_RST	14	RW
MDAR_SOFT_RST	13	RW
LVDSDIS_SOFT_RST	12	RW
BB_CAL_SOFT_RST	11	RW
DCX0_LC_SOFT_RST	10	RW
AP_TMR2_SOFT_RST	9	RW
AP_TMR1_SOFT_RST	8	RW
CA7_WDG_SOFT_RST	7	RW
AON_DMA_SOFT_RST	6	RW
AVS_SOFT_RST	5	RW
DMC_PHY_SOFT_RST	4	RW
GPU_THMA_SOFT_RST	3	RW
ARM_THMA_SOFT_RST	2	RW
THM_SOFT_RST	1	RW
PMU_SOFT_RST	0	RW

10.1.5. APB_RTC_EB (0x402e0010)

Symbol	Bit range	R/W
CP0_LTE_EB	19	RW
BB_CAL_RTC_EB	18	RW
DCX0_LC_RTC_EB	17	RW
AP_TMR2_RTC_EB	16	RW
AP_TMR1_RTC_EB	15	RW
GPU_THMA_RTC_AUTO_EN	14	RW
ARM_THMA_RTC_AUTO_EN	13	RW
GPU_THMA_RTC_EB	12	RW
ARM_THMA_RTC_EB	11	RW
THM_RTC_EB	10	RW
CA7_WDG_RTC_EB	9	RW
AP_WDG_RTC_EB	8	RW
EIC_RTCDV5_EB	7	RW
EIC_RTC_EB	6	RW
AP_TMR0_RTC_EB	5	RW
AON_TMR_RTC_EB	4	RW
AP_SYST_RTC_EB	3	RW
AON_SYST_RTC_EB	2	RW
KPD_RTC_EB	1	RW
ARCH_RTC_EB	0	RW

10.1.6. REC_26MHZ_BUF_CFG (0x402e0014)

Symbol	Bit range	R/W
PLL_PROBE_SEL	13-8	RW
REC_26MHZ_1_CUR_SEL	4	RW
REC_26MHZ_0_CUR_SEL	0	RW

10.1.7. SINDRV_CTRL (0x402e0018)

Symbol	Bit range	R/W
SINDRV_LVL	4-3	RW
SINDRV_CLIP_MODE	2	RW
SINDRV_ENA_SQUARE	1	RW
SINDRV_ENA	0	RW

10.1.8. ADA_SEL_CTRL (0x402e001c)

Symbol	Bit range	R/W
TW_MODE_SEL	3	RW
WGADC_DIV_EN	2	RW
AFCDAC_SYS_SEL	1	RW
APCDAC_SYS_SEL	0	RW

10.1.9. VBC_CTRL (0x402e0020)

Symbol	Bit range	R/W
AUDIF_CKG_AUTO_EN	20	RW
AUD_INT_SYS_SEL	19-18	RW
VBC_AFIFO_INT_SYS_SEL	17-16	RW
VBC_AD23_INT_SYS_SEL	15-14	RW
VBC_AD01_INT_SYS_SEL	13-12	RW
VBC_DA01_INT_SYS_SEL	11-10	RW
VBC_AD23_DMA_SYS_SEL	9-8	RW
VBC_AD01_DMA_SYS_SEL	7-6	RW
VBC_DA01_DMA_SYS_SEL	5-4	RW
VBC_INT_CP0_ARM_SEL	3	RW
VBC_INT_CP1_ARM_SEL	2	RW
VBC_DMA_CP0_ARM_SEL	1	RW
VBC_DMA_CP1_ARM_SEL	0	RW

10.1.10. PWR_CTRL (0x402e0024)

Symbol	Bit range	R/W
HSIC_PLL_EN	19	RW
HSIC_PHY_PD	18	RW
HSIC_PS_PD_S	17	RW
HSIC_PS_PD_L	16	RW
MIPI_DSI_PS_PD_S	15	RW
MIPI_DSI_PS_PD_L	14	RW
MIPI_CSI_4LANE_PS_PD_S	13	RW
MIPI_CSI_4LANE_PS_PD_L	12	RW
MIPI_CSI_2LANE_PS_PD_S	11	RW
MIPI_CSI_2LANE_PS_PD_L	10	RW
CA7_TS1_STOP	9	RW
CA7_TS0_STOP	8	RW
EFUSE_BIST_PWR_ON	3	RW
FORCE_DSI_PHY_SHUTDOWNZ	2	RW
FORCE_CSI_PHY_SHUTDOWNZ	1	RW
USB_PHY_PD	0	RW

10.1.11. TS_CFG (0x402e0028)

Symbol	Bit range	R/W
CSYSACK_TS_LP_2	13	RW
CSYSREQ_TS_LP_2	12	RW
CSYSACK_TS_LP_1	11	RW
CSYSREQ_TS_LP_1	10	RW
CSYSACK_TS_LP_0	9	RW
CSYSREQ_TS_LP_0	8	RW
EVENTACK_RESTARTREQ_TS01	4	RW
EVENT_RESTARTREQ_TS01	1	RW
EVENT_HALTREQ_TS01	0	RW

10.1.12. BOOT_MODE (0x402e002c)

Symbol	Bit range	R/W
ARM_JTAG_EN	13	RW
WPLL_OVR_FREQ_SEL	12	RW
PTEST_FUNC_ATSPEED_SEL	8	RW
PTEST_FUNC_MODE	7	R
USB_DLOAD_EN	4	R
ARM_BOOT_MD3	3	R
ARM_BOOT_MD2	2	R
ARM_BOOT_MD1	1	R
ARM_BOOT_MD0	0	R

10.1.13. BB_BG_CTRL (0x402e0030)

Symbol	Bit range	R/W
BB_CON_BG	22	RW
BB_BG_RSV	21-20	RW
BB_LDO_V	19-16	RW
BB_BG_RBIAS_EN	15	RW
BB_BG_IEXT_IB_EN	14	RW
BB_LDO_REFCTRL	13-12	RW
BB_LDO_AUTO_PD_EN	11	RW
BB_LDO_SLP_PD_EN	10	RW
BB_LDO_FORCE_ON	9	RW
BB_LDO_FORCE_PD	8	RW
BB_BG_AUTO_PD_EN	3	RW
BB_BG_SLP_PD_EN	2	RW
BB_BG_FORCE_ON	1	RW
BB_BG_FORCE_PD	0	RW

10.1.14. CP_ARM_JTAG_CTRL (0x402e0034)

Symbol	Bit range	R/W	Description
CP_ARM_JTAG_PIN_SEL	2-0	RW

10.1.15. PLL_SOFT_CNT_DONE (0x402e0038)

Symbol	Bit range	R/W
RC1_SOFT_CNT_DONE	13	RW
RC0_SOFT_CNT_DONE	12	RW
XTLBUF1_SOFT_CNT_DONE	9	RW
XTLBUF0_SOFT_CNT_DONE	8	RW
LVDSPLL_SOFT_CNT_DONE	4	RW
LPLL_SOFT_CNT_DONE	3	RW
TWPLL_SOFT_CNT_DONE	2	RW
DPLL_SOFT_CNT_DONE	1	RW
MPLL_SOFT_CNT_DONE	0	RW

10.1.16. DCXO_LC_REG0 (0x402e003c)

Symbol	Bit range	R/W
DCXO_LC_FLAG	8	RW
DCXO_LC_FLAG_CLR	1	RW
DCXO_LC_CNT_CLR	0	RW

10.1.17. DCXO_LC_REG1 (0x402e0040)

Symbol	Bit range	R/W	Description
DCXO_LC_CNT	31-0	RW

10.1.18. MPLL_CFG1 (0x402e0044)

Symbol	Bit range	R/W
MPLL_RES	29-28	RW
MPLL_LOCK_DONE	27	RW
MPLL_DIV_S	26	RW
MPLL_MOD_EN	25	RW
MPLL_SDM_EN	24	RW
MPLL_LPF	22-20	RW
MPLL_REFIN	19-18	RW
MPLL_IBIAS	17-16	RW
MPLL_N	10-0	RW

10.1.19. MPLL_CFG2 (0x402e0048)

Symbol	Bit range	R/W	Description
MPLL_NINT	29-24	RW
MPLL_KINT	19-0	RW

10.1.20. DPLL_CFG1 (0x402e004c)

Symbol	Bit range	R/W
DPLL_RES	29-28	RW
DPLL_LOCK_DONE	27	RW
DPLL_DIV_S	26	RW
DPLL_MOD_EN	25	RW
DPLL_SDM_EN	24	RW
DPLL_LPF	22-20	RW
DPLL_REFIN	19-18	RW
DPLL_IBIAS	17-16	RW
DPLL_N	10-0	RW

10.1.21. DPLL_CFG2 (0x402e0050)

Symbol	Bit range	R/W	Description
DPLL_NINT	29-24	RW
DPLL_KINT	19-0	RW

10.1.22. TWPLL_CFG1 (0x402e0054)

Symbol	Bit range	R/W
TWPLL_RES	29-28	RW
TWPLL_LOCK_DONE	27	RW
TWPLL_DIV_S	26	RW
TWPLL_MOD_EN	25	RW
TWPLL_SDM_EN	24	RW
TWPLL_LPF	22-20	RW
TWPLL_REFIN	19-18	RW
TWPLL_IBIAS	17-16	RW
TWPLL_N	10-0	RW

10.1.23. TWPLL_CFG2 (0x402e0058)

Symbol	Bit range	R/W	Description
TWPLL_NINT	29-24	RW
TWPLL_KINT	19-0	RW

10.1.24. LTEPLL_CFG1 (0x402e005c)

Symbol	Bit range	R/W
LTEPLL_RES	29-28	RW
LTEPLL_LOCK_DONE	27	RW
LTEPLL_DIV_S	26	RW
LTEPLL_MOD_EN	25	RW
LTEPLL_SDM_EN	24	RW
LTEPLL_LPF	22-20	RW
LTEPLL_REFIN	19-18	RW
LTEPLL_IBIAS	17-16	RW
LTEPLL_N	10-0	RW

10.1.25. LTEPLL_CFG2 (0x402e0060)

Symbol	Bit range	R/W	Description
LTEPLL_NINT	29-24	RW
LTEPLL_KINT	19-0	RW

10.1.26. LVDSDISPLL_CFG1 (0x402e0064)

Symbol	Bit range	R/W
LVDSDISPLL_RES	29-28	RW
LVDSDISPLL_LOCK_DONE	27	RW
LVDSDISPLL_DIV_S	26	RW
LVDSDISPLL_MOD_EN	25	RW
LVDSDISPLL_SDM_EN	24	RW
LVDSDISPLL_LPF	22-20	RW
LVDSDISPLL_REFIN	19-18	RW
LVDSDISPLL_IBIAS	17-16	RW
LVDSDISPLL_N	10-0	RW

10.1.27. LVDSDISPLL_CFG2 (0x402e0068)

Symbol	Bit range	R/W	Description
LVDSDISPLL_NINT	29-24	RW
LVDSDISPLL_KINT	19-0	RW

10.1.28. AON_REG_PROT (0x402e006c)

Protect register (big endian)

Symbol	Bit range	R/W	Description
LDSP_CTRL_PROT	31	RW
REG_PROT_VAL	15-0	RW

10.1.29. LDSP_BOOT_EN (0x402e0070)

DSP boot enable

Symbol	Bit range	R/W	Description
FRC_CLK_LDSP_EN	1	RW
LDSP_BOOT_EN	0	RW

10.1.30. LDSP_BOOT_VEC (0x402e0074)

DSP boot vector

Symbol	Bit range	R/W	Description
LDSP_BOOT_VECTOR	31-0	RW

10.1.31. LDSP_RST (0x402e0078)

DSP reset

Symbol	Bit range	R/W	Description
LDSP_SYS_SRST	1	RW
LDSP_CORE_SRST_N	0	RW

10.1.32. LDSP_MTX_CTRL1 (0x402e007c)

Symbol	Bit range	R/W	Description
LDSP_MTX_CTRL1	31-0	RW

10.1.33. LDSP_MTX_CTRL2 (0x402e0080)

Symbol	Bit range	R/W	Description
LDSP_MTX_CTRL2	31-0	RW

10.1.34. LDSP_MTX_CTRL3 (0x402e0084)

Symbol	Bit range	R/W	Description
LDSP_MTX_CTRL3	31-0	RW

10.1.35. AON_CGM_CFG (0x402e0088)

Symbol	Bit range	R/W
PROBE_CKG_DIV	31-28	RW
AUX2_CKG_DIV	27-24	RW
AUX1_CKG_DIV	23-20	RW
AUX0_CKG_DIV	19-16	RW
PROBE_CKG_SEL	15-12	RW
AUX2_CKG_SEL	11-8	RW
AUX1_CKG_SEL	7-4	RW
AUX0_CKG_SEL	3-0	RW

10.1.36. LACC_MTX_CTRL (0x402e008c)

Symbol	Bit range	R/W	Description
LACC_MTX_CTRL	31-0	RW

10.1.37. CORTEX_MTX_CTRL1 (0x402e0090)

Symbol	Bit range	R/W	Description
CORTEX_MTX_CTRL1	31-0	RW

10.1.38. CORTEX_MTX_CTRL2 (0x402e0094)

Symbol	Bit range	R/W	Description
CORTEX_MTX_CTRL2	31-0	RW

10.1.39. CORTEX_MTX_CTRL3 (0x402e0098)

Symbol	Bit range	R/W	Description
CORTEX_MTX_CTRL3	15-0	RW

10.1.40. CA5_TCLK_DLY_LEN (0x402e009c)

Symbol	Bit range	R/W	Description
CA5_TCLK_DLY_LEN	15-0	RW

10.1.41. AON_CHIP_ID_H (0x402e00f8)

Symbol	Bit range	R/W	Description
AON_CHIP_ID_H	31-0	R	0x53686172 ('Shar')

10.1.42. AON_CHIP_ID_L (0x402e00fc)

Symbol	Bit range	R/W	Description
AON_CHIP_ID_L	31-0	R	0x6b4c5300 ('kLS\0')

10.1.43. CCIR_RCVR_CFG (0x402e0100)

Symbol	Bit range	R/W
ANALOG_PLL_RSV	23-16	RW
ANALOG_TESTMUX	15-8	RW
CCIR_SE	1	RW
CCIR_IE	0	RW

10.1.44. PLL_BG_CFG (0x402e0108)

Symbol	Bit range	R/W
PLL_BG_RSV	5-4	RW
PLL_BG_RBIAS_EN	3	RW
PLL_BG_PD	2	RW
PLL_BG_IEXT_IBEN	1	RW
PLL_CON_BG	0	RW

10.1.45. LVDSDIS_SEL (0x402e010c)

Symbol	Bit range	R/W	Description
LVDSDIS_LOG_SEL	2-1	RW
LVDSDIS_DBG_SEL	0	RW

10.1.46. DJTAG_MUX_SEL (0x402e0110)

Symbol	Bit range	R/W
DJTAG_CODEC_SEL	7	RW
DJTAG_AON_SEL	6	RW
DJTAG_PUB_SEL	5	RW
DJTAG_CP1_SEL	4	RW
DJTAG_CP0_SEL	3	RW
DJTAG_GPU_SEL	2	RW
DJTAG_MM_SEL	1	RW
DJTAG_AP_SEL	0	RW

10.1.47. ARM7_SYS_SOFT_RST (0x402e0114)

Symbol	Bit range	R/W	Description
ARM7_SYS_SOFT_RST	4	RW
ARM7_CORE_SOFT_RST	0	RW

10.1.48. CP1_CP0_ADDR_MSB (0x402e0118)

Symbol	Bit range	R/W	Description
CP1_CP0_ADDR_MSB	3-0	RW

10.1.49. AON_DMA_INT_EN (0x402e011c)

Symbol	Bit range	R/W
AON_DMA_INT_ARM7_EN	6	RW
AON_DMA_INT_CP1_DSP_EN	5	RW
AON_DMA_INT_CP1_CA5_EN	4	RW
AON_DMA_INT_CP0_DSP_1_EN	3	RW
AON_DMA_INT_CP0_DSP_0_EN	2	RW
AON_DMA_INT_CP0_ARM9_0_EN	1	RW
AON_DMA_INT_AP_EN	0	RW

10.1.50. EMC_AUTO_GATE_EN (0x402e0120)

Symbol	Bit range	R/W
CP1_PUB_AUTO_GATE_EN	19	RW
CP0_PUB_AUTO_GATE_EN	18	RW
AP_PUB_AUTO_GATE_EN	17	RW
AON_APB_PUB_AUTO_GATE_EN	16	RW
CP1_EMC_AUTO_GATE_EN	3	RW
CP0_EMC_AUTO_GATE_EN	2	RW
AP_EMC_AUTO_GATE_EN	1	RW
CA7_EMC_AUTO_GATE_EN	0	RW

10.1.51. APB_ARM7_CFG_BUS (0x402e0124)

Symbol	Bit range	R/W	Description
ARM7_CFG_BUS_SLEEP	0	RW

10.1.52. RTC4M_0_CFG (0x402e0128)

Symbol	Bit range	R/W
RTC4M0_RSV	23-16	RW
RTC4M0_I_C	11-8	RW
RTC4M0_CAL_DONE	6	RW
RTC4M0_CAL_START	5	RW
RTC4M0_CHOP_EN	4	RW
RTC4M0_FORCE_EN	1	RW
RTC4M0_AUTO_GATE_EN	0	RW

10.1.53. RTC4M_1_CFG (0x402e012c)

Symbol	Bit range	R/W
RTC4M1_RSV	23-16	RW
RTC4M1_I_C	11-8	RW
RTC4M1_CAL_DONE	6	RW
RTC4M1_CAL_START	5	RW
RTC4M1_CHOP_EN	4	RW
RTC4M1_FORCE_EN	1	RW
RTC4M1_AUTO_GATE_EN	0	RW

10.1.54. APB_RST2 (0x402e0130)

Symbol	Bit range	R/W
CODEC_DJTAG_SOFT_RST	7	RW
AON_DJTAG_SOFT_RST	6	RW
PUB_DJTAG_SOFT_RST	5	RW
GPU_DJTAG_SOFT_RST	4	RW
MM_DJTAG_SOFT_RST	3	RW
CP1_DJTAG_SOFT_RST	2	RW
CP0_DJTAG_SOFT_RST	1	RW
AP_DJTAG_SOFT_RST	0	RW

10.1.55. AP_WPROT_EN1 (0x402e3004)

Symbol	Bit range	R/W	Description
AP_AWADDR_WPROT_EN1	31-0	RW

10.1.56. CP0_WPROT_EN1 (0x402e3008)

Symbol	Bit range	R/W	Description
CP0_AWADDR_WPROT_EN1	31-0	RW

10.1.57. CP1_WPROT_EN1 (0x402e300c)

Symbol	Bit range	R/W	Description
CP1_AWADDR_WPROT_EN1	31-0	RW

10.1.58. IO_DLY_CTRL (0x402e3014)

Symbol	Bit range	R/W
CLK_CCIR_DLY_SEL	11-8	RW
CLK_CP1DSP_DLY_SEL	7-4	RW
CLK_CP0DSP_DLY_SEL	3-0	RW

10.1.59. AP_WPROT_EN0 (0x402e3018)

Symbol	Bit range	R/W	Description
AP_AWADDR_WPROT_EN1	31-0	RW

10.1.60. AP_WPROT_EN0 (0x402e3018)

Symbol	Bit range	R/W	Description
AP_AWADDR_WPROT_EN0	31-0	RW

10.1.61. CP0_WPROT_EN0 (0x402e3020)

Symbol	Bit range	R/W	Description
CP0_AWADDR_WPROT_EN0	31-0	RW

10.1.62. CP1_WPROT_EN0 (0x402e3024)

Symbol	Bit range	R/W	Description
CP1_AWADDR_WPROT_EN0	31-0	RW

10.1.63. PMU_RST_MONITOR (0x402e302c)

Symbol	Bit range	R/W	Description
PMU_RST_MONITOR	31-0	RW

10.1.64. THM_RST_MONITOR (0x402e3030)

Symbol	Bit range	R/W	Description
THM_RST_MONITOR	31-0	RW

10.1.65. AP_RST_MONITOR (0x402e3034)

Symbol	Bit range	R/W	Description
AP_RST_MONITOR	31-0	RW

10.1.66. CA7_RST_MONITOR (0x402e3038)

Symbol	Bit range	R/W	Description
AP_RST_MONITOR	31-0	RW

10.1.67. BOND_OPT0 (0x402e303c)

Symbol	Bit range	R/W	Description
BOND_OPTION0	31-0	RW

10.1.68. BOND_OPT1 (0x402e3040)

Symbol	Bit range	R/W	Description
BOND_OPTION1	31-0	RW

10.1.69. RES_REG0 (0x402e3044)

Symbol	Bit range	R/W	Description
RES_REG0	31-0	RW

10.1.70. RES_REG1 (0x402e3048)

Symbol	Bit range	R/W	Description
RES_REG1	31-0	RW

10.1.71. AON_QOS_CFG (0x402e304c)

Symbol	Bit range	R/W
QOS_R_GPU	15-12	RW
QOS_W_GPU	11-8	RW
QOS_R_GSP	7-4	RW
QOS_W_GSP	3-0	RW

10.1.72. BB_LDO_CAL_START (0x402e3050)

Symbol	Bit range	R/W	Description
BB_LDO_CAL_START	0	RW

10.1.73. AON_MTX_PROT_CFG (0x402e3058)

Symbol	Bit range	R/W	Description
HPROT_DMAW	7-4	RW
HPROT_DMAR	3-0	RW

10.1.74. LVDS_CFG (0x402e3060)

Symbol	Bit range	R/W
LVDSDIS_TXCLKDATA	22-16	RW
LVDSDIS_TXCOM	13-12	RW
LVDSDIS_TXSLEW	11-10	RW
LVDSDIS_TXSW	9-8	RW
LVDSDIS_TXRERSER	7-3	RW
LVDSDIS_PRE_EMP	2-1	RW
LVDSDIS_TXPD	0	RW

10.1.75. PLL_LOCK_OUT_SEL (0x402e3064)

Symbol	Bit range	R/W
SLEEP_PLLLOCK_SEL	7	RW
PLL_LOCK_SEL	6-4	RW
SLEEP_DBG_SEL	3-0	RW

10.1.76. RTC4M_RC_VAL (0x402e3068)

Symbol	Bit range	R/W
RTC4M1_RC_SEL	31	RW
RTC4M1_RC_VAL	24-16	RW
RTC4M0_RC_SEL	15	RW
RTC4M0_RC_VAL	8-0	RW

10.1.77. AON_APB_RSV (0x402e30f0)

Symbol	Bit range	R/W	Description
AON_APB_RSV	31-0	RW

10.1.78. AON_CHIP_ID (0x402e30??)

Symbol	Bit range	R/W	Description
AON_CHIP_ID	31-0	RW

11. UART

Instance	Base address
UART0	0x70000000
UART1	0x70100000
UART2	0x70200000
UART3	0x70300000
UART4	0x70400000

Guessed Tx and Rx FIFO depth: 0x40 bytes

11.1. Registers

Symbol	Offset	Description
TXD	0x00	Tx data
RXD	0x04	Rx data
STS0	0x08	Status 0
STS1	0x0c	Status 1
IEN	0x10	Interrupt enable
ICLR	0x14	Interrupt clear
CTL0	0x18	Control 0
CTL1	0x1c	Control 1
CTL2	0x20	Control 2
CLKD0	0x24	Clock divider 0
CLKD1	0x28	Clock divider 1
STS2	0x2c	Status 2

11.1.1. TXD (0x00)

Tx data register.

Symbol	Bit range	R/W	Description
DATA	7-0	W	Data byte to send

11.1.2. RXD (0x04)

Rx data register.

Symbol	Bit range	R/W	Description
DATA	7-0	W	Data byte received

11.1.3. STS0 (0x08)

Line status register.

Symbol	Bit range	R/W	Description

11.1.4. STS1 (0x0c)

FIFO status register.

Symbol	Bit range	R/W	Description
TX_LEVEL	15-8	R	Number of bytes in Tx FIFO
RX_LEVEL	7-0	R	Number of bytes in Rx FIFO

11.1.5. IEN (0x10)

Interrupt enable register.

Symbol	Bit range	R/W	Description

12. AP APB control

Base address
0x71300000

12.1. Registers

Symbol	Offset	Description
APB_EB	0x0000	APB enable bits
APB_RST	0x0004	APB reset bits
APB_MISC_CTRL	0x0008	APB misc control bits

12.1.1. APB_EB (0x71300000)

Symbol	Bit range	R/W
INTC3_EB	22	RW
INTC2_EB	21	RW
INTC1_EB	20	RW
INTC0_EB	19	RW
AP_CKG_EB	18	RW
UART4_EB	17	RW
UART3_EB	16	RW
UART2_EB	15	RW
UART1_EB	14	RW
UART0_EB	13	RW
I2C4_EB	12	RW
I2C3_EB	11	RW
I2C2_EB	10	RW
I2C1_EB	9	RW
I2C0_EB	8	RW
SPI2_EB	7	RW
SPI1_EB	6	RW
SPI0_EB	5	RW
IIS3_EB	4	RW
IIS2_EB	3	RW
IIS1_EB	2	RW
IIS0_EB	1	RW
SIM0_EB	0	RW

12.1.2. APB_RST (0x71300004)

Symbol	Bit range	R/W
INTC3_RST	22	RW
INTC2_RST	21	RW
INTC1_RST	20	RW
INTC0_RST	19	RW
AP_CKG_RST	18	RW
UART4_RST	17	RW
UART3_RST	16	RW
UART2_RST	15	RW
UART1_RST	14	RW
UART0_RST	13	RW
I2C4_RST	12	RW
I2C3_RST	11	RW
I2C2_RST	10	RW
I2C1_RST	9	RW
I2C0_RST	8	RW
SPI2_RST	7	RW
SPI1_RST	6	RW
SPI0_RST	5	RW
IIS3_RST	4	RW
IIS2_RST	3	RW
IIS1_RST	2	RW
IIS0_RST	1	RW
SIM0_RST	0	RW

12.1.3. APB_MISC_CTRL (0x71300008)

Symbol	Bit range	R/W	Description
SIM_CLK_POLARITY	1	RW
FMARK_POLARITY_INV	0	RW

13. INTC

Instance	Base address
INTC0	0x71400000
INTC1	0x71500000
INTC2	0x71600000
INTC3	0x71700000

Interrupt index	Interrupt name	INTC chip	INTC bit	IRQ MUX bit
0	SPECIAL_LATCH	INTC0	0	N/A
1	SOFT_TRIGGERED0_INT	INTC0	1	N/A
2	SER0_INT	INTC0	2	N/A
3	SER1_INT	INTC0	3	N/A
4	SER2_INT	INTC0	4	N/A
5	SER3_INT	INTC0	5	N/A
6	SER4_INT	INTC0	6	N/A
7	SPI0_INT	INTC0	7	N/A
8	SPI1_INT	INTC0	8	N/A
9	SPI2_INT	INTC0	9	N/A
10	SIM0_INT	INTC0	10	N/A
11	I2C0_INT	INTC0	11	N/A
12	I2C1_INT	INTC0	12	N/A
13	I2C2_INT	INTC0	13	N/A
14	I2C3_INT	INTC0	14	N/A
15	I2C4_INT	INTC0	15	N/A
16	IIS0_INT	INTC0	16	N/A
17	IIS1_INT	INTC0	17	N/A
18	IIS2_INT	INTC0	18	N/A
19	IIS3_INT	INTC0	19	N/A
20	REQ_AUD_INT	INTC0	20	4
21	REQ_AUD_VBC_AFIFO_INT	INTC0	21	3
22	REQ_AUD_VBC_DA_INT	INTC0	22	3
23	REQ_AUD_VBC_AD01_INT	INTC0	23	3
24	REQ_AUD_VBC_AD23_INT	INTC0	24	3
25	ADI_INT	INTC0	25	4
26	THM_INT	INTC0	26	9
27	FM_INT	INTC0	27	N/A
28	AONTMR0_INT	INTC0	28	2
29	APTMR0_INT	INTC0	29	2
30	AONSYST_INT	INTC0	30	2
31	APSYST_INT	INTC0	31	2
32	N/A	N/A	N/A	N/A
33	N/A	N/A	N/A	N/A
34	AONI2C_INT	INTC1	2	4
35	GPIO_INT	INTC1	3	4
36	KPD_INT	INTC1	4	4
37	EIC_INT	INTC1	5	31
38	ANA_INT	INTC1	6	4
39	GPU_INT	INTC1	7	6
40	CSI_INT0	INTC1	8	5
41	CSI_INT1	INTC1	9	5
42	JPG_INT	INTC1	10	5
43	VSP_INT	INTC1	11	5
44	ISP_INT	INTC1	12	5
45	DCAM_INT	INTC1	13	5
46	DISPC0_INT	INTC1	14	N/A
47	DISPC1_INT	INTC1	15	N/A
48	DSI0_INT	INTC1	16	N/A
49	DSI1_INT	INTC1	17	N/A
50	DMA_INT	INTC1	18	N/A
51	GSP_INT	INTC1	19	N/A
52	GPS_INT	INTC1	20	N/A
53	GPS_RTCEXP_INT	INTC1	21	N/A
54	GPS_WAKEUP_INT	INTC1	22	N/A
55	USBD_INT	INTC1	23	N/A
56	NFC_INT	INTC1	24	N/A
57	SDIO0_INT	INTC1	25	N/A
58	SDIO1_INT	INTC1	26	N/A
59	SDIO2_INT	INTC1	27	N/A
60	EMMC_INT	INTC1	28	N/A
61	BM0_INT	INTC1	29	N/A
62	BM1_INT	INTC1	30	N/A
63	BM2_INT	INTC1	31	N/A
64	N/A	N/A	N/A	N/A
65	N/A	N/A	N/A	N/A
66	DRM_INT	INTC2	2	N/A
67	CP0_DSP_INT	INTC2	3	N/A
68	CP0_MCU0_INT	INTC2	4	N/A
69	CP0_MCU1_INT	INTC2	5	12
70	CP1_DSP_INT	INTC2	6	N/A
71	CP1_MCU0_INT	INTC2	7	N/A
72	CP1_MCU1_INT	INTC2	8	N/A
73	CP2_INT0_INT	INTC2	9	N/A
74	CP2_INT1_INT	INTC2	10	N/A
75	CP0_DSP_FIQ_INT	INTC2	11	N/A
76	CP0_MCU_FIQ0_INT	INTC2	12	N/A
77	CP0_MCU_FIQ1_INT	INTC2	13	N/A
78	CP1_MCU_FIQ_INT	INTC2	14	N/A
79	N/A	N/A	N/A	N/A
80	N/A	N/A	N/A	N/A
81	N/A	N/A	N/A	N/A
82	N/A	N/A	N/A	N/A
83	CP0_WDG_INT	INTC2	19	7
84	CP1_WDG_INT	INTC2	20	7
85	CP2_WDG_INT	INTC2	21	N/A
86	AXI_BM_PUB_INT	INTC2	22	10
87	N/A	N/A	N/A	N/A
88	N/A	N/A	N/A	N/A
89	N/A	N/A	N/A	N/A
90	N/A	N/A	N/A	N/A
91	N/A	N/A	N/A	N/A
92	NPMUIRQ0_INT	INTC2	28	N/A
93	NPMUIRQ1_INT	INTC2	29	N/A
94	NPMUIRQ2_INT	INTC2	30	N/A
95	NPMUIRQ3_INT	INTC2	31	N/A
96	N/A	N/A	N/A	N/A
97	N/A	N/A	N/A	N/A
98	CA7COM0_INT	INTC3	2	N/A
99	CA7COM1_INT	INTC3	3	N/A
100	CA7COM2_INT	INTC3	4	N/A
101	CA7COM3_INT	INTC3	5	N/A
102	NCNTV0_INT	INTC3	6	N/A
103	NCNTV1_INT	INTC3	7	N/A
104	NCNTV2_INT	INTC3	8	N/A
105	NCNTV3_INT	INTC3	9	N/A
106	NCNTHP0_INT	INTC3	10	N/A
107	NCNTHP1_INT	INTC3	11	N/A
108	NCNTHP2_INT	INTC3	12	N/A
109	NCNTHP3_INT	INTC3	13	N/A
110	NCNTPN0_INT	INTC3	14	N/A
111	NCNTPN1_INT	INTC3	15	N/A
112	NCNTPN2_INT	INTC3	16	N/A
113	NCNTP3_INT	INTC3	17	N/A
114	NCNTPS0_INT	INTC3	18	N/A
115	NCNTPS1_INT	INTC3	19	N/A
116	NCNTPS2_INT	INTC3	20	N/A
117	NCNTPS3_INT	INTC3	21	N/A
118	APTMR1_INT	INTC3	22	2
119	APTMR2_INT	INTC3	23	2
120	APTMR3_INT	INTC3	24	2
121	APTMR4_INT	INTC3	25	2
122	AVS_INT	INTC3	26	9
123	APWDG_INT	INTC3	27	8
124	CA7WDG_INT	INTC3	28	8

13.1. Registers

Symbol	Offset	Description
IRQ_MSK	0x00	IRQ status after masking
IRQ_RAW	0x04	IRQ status before masking
IRQ_EN	0x08	IRQ enable register
IRQ_DIS	0x0c	IRQ disable register
IRQ_SOFT	0x10
FIQ_MSK	0x20	FIQ status after masking
FIQ_RAW	0x24	FIQ status before masking
FIQ_EN	0x28	FIQ enable register
FIQ_DIS	0x2c	FIQ disable register

13.1.1. IRQ_MSK (0x00)

Symbol	Bit range	R/W	Description
IRQ_MSK	31-0	R	IRQ status after masking

13.1.2. IRQ_RAW (0x04)

Symbol	Bit range	R/W	Description
IRQ_RAW	31-0	R	IRQ status before masking

13.1.3. IRQ_EN (0x08)

Symbol	Bit range	R/W	Description
IRQ_EN	31-0	W	IRQ enable register

13.1.4. IRQ_DIS (0x0c)

Symbol	Bit range	R/W	Description
IRQ_DIS	31-0	W	IRQ disable register

13.1.5. IRQ_SOFT (0x10)

Symbol	Bit range	R/W	Description

13.1.6. FIQ_MSK (0x00)

Symbol	Bit range	R/W	Description
FIQ_MSK	31-0	R	FIQ status after masking

13.1.7. FIQ_RAW (0x04)

Symbol	Bit range	R/W	Description
FIQ_RAW	31-0	R	FIQ status before masking

13.1.8. FIQ_EN (0x08)

Symbol	Bit range	R/W	Description
FIQ_EN	31-0	W	FIQ enable register

13.1.9. FIQ_DIS (0x0c)

Symbol	Bit range	R/W	Description
FIQ_DIS	31-0	W	FIQ disable register