1. About this document

This document is an effort to document the Comcerto 2000 SoC from Mindspeed technologies (rebranded as Freescale/NXP QorIQ LS1024A after acquisition by Freescale, then by NXP).

The information in this document comes only from public sources, such as the official public datasheet, datasheets from other chips using the same IP blocks, GPL'd source code, and experimentation on real hardware.

Be aware that because of this, this document potentially contains a lot of imprecise, if not downright incorrect information.

After acquisition by Freescale, the C2000 SoC was rebranded QorIQ LayerScape 1024A (or LS1024A for short).

2. Memory map

2.1. AXI peripherals

Map of the physical memory and I/O space as seen by the Cortex A9 CPU.

Range	Region size (w/o mirrors)	Description
0x00000000-0x80000000	Variable	DDR
0x80000000-0x82ffffff	0x01000000?	ACP (Accelerator Coherency Port)
0x83000000-0x85ffffff	0x00010000	IRAM
0x90000000-0x903fffff	0x00008000	IBR
0x90400000-0x90ffffff	0x00c00000	APB bridge
0x91000000-0x91ffffff	0x00000100	SEMA (hardware semaphore)
0x92000000-0x92ffffff	0x00040000	USB2.0
0x93000000-0x93ffffff	?	TRUSTZONE
0x94000000-0x94ffffff	?	DPI0
0x95000000-0x95ffffff	?	DPI1
0x96000000-0x96ffffff	0x01000000	DUSI
0x96000000-0x962fffff	0x00000400	DMA?
0x96300000-0x963fffff	0x00100000	UART0
0x96400000-0x964fffff	0x00100000	UART1
0x96500000-0x965fffff	0x00100000	SPI
0x96600000-0x966fffff	0x00100000	I2S?
0x97000000-0x97ffffff	0x00000400	DDRCONFIG
0x98000000-0x98ffffff	0x200	PCIe0
0x99000000-0x99ffffff	0x200	PCIe1
0x9a000000-0x9affffff	?	IPSEC
0x9b000000-0x9bffffff	?	SPACC PDU
0x9c000000-0x9cffffff	?	PFE
0x9d000000-0x9dffffff	?	SATA
0x9e000000-0x9effffff	?	DECT
0x9f000000-0x9fffffff	0x10000000	USB3.0
0xa0000000-0xafffffff	0x10000000	PCIe0 slave
0xb0000000-0xbfffffff	0x10000000	PCIe1 slave
0xc0000000-0xcfffffff	0x10000000	EXP
0xcfff0000-0xcfffffff	0x00010000?	EXP_ECC
0x-0x	0x	?
0xfff00000-0xfff1ffff	?	Cortex A9 peripherals

2.2. APB peripherals

I/O layout of APB peripherals region.

Range	Region size (w/o mirrors)	Description
0x90400000-0x9040ffff	0x	TDM
0x90410000-0x9041ffff	0x	USB PHY SerDes
0x90420000-0x9042ffff	0x	TDMA
0x90430000-0x9043ffff	0x	Reserved 2
0x90440000-0x9044ffff	0x	Reserved 3
0x90450000-0x9045ffff	0x	Timer
0x90460000-0x9046ffff	0x	PCIe SATA & USB CTRL
0x90470000-0x9047ffff	0x	GPIO
0x90480000-0x9048ffff	0x	Reserved 5
0x90490000-0x90493fff	0x	UART0
0x90494000-0x90497fff	0x	Reserved 6
0x90498000-0x9049bfff	0x1000	SPI
0x9049c000-0x9049ffff	0x20	I2C
0x904a0000-0x904affff	0x800	USB3.0 PHY
0x904b0000-0x904bffff	0x400	CLKCORE
0x904c0000-0x904cffff	0x	Reserved 7
0x904d0000-0x904dffff	0x	Reserved 8
0x904e0000-0x904effff	0x	RTC
0x904f0000-0x904fffff	0x	OTP
0x90500000-0x9050ffff	0x	HFE wrapper
0x90510000-0x9051ffff	0x	Reserved 10
0x90520000-0x9052ffff	0x	Reserved 11
0x90530000-0x9053ffff	0x	Reserved 12
0x90540000-0x9054ffff	0x	Reserved 13
0x90550000-0x9055ffff	0x	Reserved 14
0x90560000-0x9056ffff	0x	Reserved 15
0x90570000-0x9057ffff	0x	Reserved 16
0x90580000-0x9058ffff	0x	Reserved 17
0x90590000-0x9059ffff	0x	SerDes CFG
0x905a0000-0x905affff	0x	EXP CONF
0x905b0000-0x905bffff	0x	DDR PHY
0x905c0000-0x905cffff	0x	Reserved 20
0x905d0000-0x905dffff	0x	TDMA2
0x905e0000-0x905?????	0x	MDMA
0x90600000-0x906?????	0x	A9 CoreSight
0x905-0x905	0x	?

2.3. MPCore peripherals

I/O layout of Cortex A9 peripherals region.

Range	Region size (w/o mirrors)	Description
0xfff00000-0xfff000ff	0x100	A9 SCU
0xfff00100-0xfff001ff	0x100?	A9 Interrupt controller INT
0xfff00200-0xfff002ff	0x100?	A9 Global Timer
0xfff00600-0xfff006ff	0x100?	A9 Timer
0xfff01000-0xfff010ff	0x1000	A9 Interrupt controller DIST
0xfff10000-0xfff1ffff	?	L2 cache controller

3. GPIO and misc. system registers

The C2000 chip features up to 64 GPIOs:

Pins 0-15 are dedicated GPIO pins by default, pins 16-63 are assigned to other functions par default.
Pins 0-3 are dedicated GPIO pins with no other function.
Pins 4-63 are muxed with GPIO and other functions.
Pins 0-7 can be configured as interrupt source
- Edge sensitive: rising, falling or both
- Level sensitive
- interrupts are provided to:
  - the A9 subsystem
  - the Util-PE block
  - the CSS block
Pins 0-15 can drive up to 10mA, which is sufficient to directly control a LED. Otherwise, an external LED driver is required.

GPIO-related registers in this block control:

Pin muxing (GPIO or function selection)
GPIO direction (input, output)
Set GPIO output value or read input value
Interrupt source configuration

Other registers:

processor to processor (PTP) IRQs
power management unit (PMU) IRQs
pads configuration (drive strength, slew rate, internal pull-up/down, Schmitt trigger inputs)
hardware IDs
fabric configuration
misc. Cortex A9 configuration
debugging
BIST registers
DDR controller

3.1. Pin muxing

As documented in the datasheet, augmented with what was found in the code:

Location	Signal symbol	Option 1	Option 2	Option 3	Option 4
P1	gem0_rxd0	RGMII0_RXD0	RMII0_RXD0	N/A	N/A
N5	gem0_rxd1	RGMII0_RXD1	RMII0_RXD1	N/A	N/A
N4	gem0_rxd2	RGMII0_RXD2	RMII0_RX_ER	N/A	N/A
N3	gem0_rxd3	RGMII0_RXD3	N/A	N/A	N/A
N2	gem0_rx_ctl	RGMII0_RX_CTL	RMII0_CRS_DV	N/A	N/A
N1	gem0_rxc	RGMII0_RXC	RMII0_CLK	N/A	N/A
R2	gem0_txd0	RGMII0_TXD0	RMII0_TXD0	N/A	N/A
R1	gem0_txd1	RGMII0_TXD1	RMII0_TXD1	N/A	N/A
P5	gem0_txd2	RGMII0_TXD2	N/A	N/A	N/A
P4	gem0_txd3	RGMII0_TXD3	N/A	N/A	N/A
P3	gem0_tx_ctl	RGMII0_TX_CTL	RMII0_TX_EN	N/A	N/A
P2	gem0_txc	RGMII0_TXC	N/A	N/A	N/A
U2	gem1_rxd0	RGMII1_RXD0	RMII1_RXD0	N/A	N/A
U1	gem1_rxd1	RGMII1_RXD1	RMII1_RXD1	N/A	N/A
T4	gem1_rxd2	RGMII1_RXD2	RMII1_RX_ER	N/A	N/A
T3	gem1_rxd3	RGMII1_RXD3	N/A	N/A	N/A
T2	gem1_rx_ctl	RGMII1_RX_CTL	RMII1_CRS_DV	N/A	N/A
T1	gem1_rxc	RGMII1_RXC	RMII1_CLK	N/A	N/A
W1	gem1_txd0	RGMII1_TXD0	RMII1_TXD0	N/A	N/A
V2	gem1_txd1	RGMII1_TXD1	RMII1_TXD1	N/A	N/A
V1	gem1_txd2	RGMII1_TXD2	N/A	N/A	N/A
U5	gem1_txd3	RGMII1_TXD3	N/A	N/A	N/A
U4	gem1_tx_ctl	RGMII1_TX_CTL	RMII1_TX_EN	N/A	N/A
U3	gem1_txc	RGMII1_TXC	N/A	N/A	N/A
Y2	gem2_rxd0	RGMII2_RXD0	RMII2_RXD0	dect_sdata_in	N/A
Y1	gem2_rxd1	RGMII2_RXD1	RMII2_RXD1	dect_sync_match	N/A
W5	gem2_rxd2	RGMII2_RXD2	RMII2_RX_ER	dect_sen	N/A
W4	gem2_rxd3	RGMII2_RXD3	N/A	dect_sdata_out	N/A
W3	gem2_rx_ctl	RGMII2_RX_CTL	RMII2_CRS_DV	i2s_bclk	N/A
W2	gem2_rxc	RGMII2_RXC	RMII2_CLK	i2s_sdo	N/A
AB1	gem2_txd0	RGMII2_TXD0	RMII2_TXD0	dect_slot_ctrl	N/A
AA2	gem2_txd1	RGMII2_TXD1	RMII2_TXD1	dect_radio_en	N/A
AA1	gem2_txd2	RGMII2_TXD2	N/A	i2s_codclko	N/A
Y5	gem2_txd3	RGMII2_TXD3	N/A	i2s_codclki	N/A
Y4	gem2_tx_ctl	RGMII2_TX_CTL	RMII2_TX_EN	i2s_lrclk	N/A
Y3	gem2_txc	RGMII2_TXC	N/A	i2s_sdi	N/A
AB2	gem2_refclk	GEM2_REFCLK	N/A	dect_tr_data	N/A
C5	gpio00	gpio00	N/A	N/A	N/A
AC4	gpio01	gpio01	N/A	N/A	N/A
AD3	gpio02	gpio02	N/A	N/A	N/A
AC3	gpio03	gpio03	N/A	N/A	N/A
Y24	gpio04	gpio04	tim_pwm0	N/A	N/A
Y25	gpio05	gpio05	tim_pwm1	N/A	N/A
E4	gpio06	gpio06	tim_pwm2	sata0_act_led	N/A
D4	gpio07	gpio07	tim_pwm3	sata0_cp_pod	N/A
AC19	gpio08	gpio08	N/A	uart0_rx	N/A
AB19	gpio09	gpio09	N/A	uart0_tx	N/A
AE20	gpio10	gpio10	N/A	uart0_rts_n	dect0
AD20	gpio11	gpio11	N/A	uart0_cts_n	dect2
AC20	gpio12	gpio12	tim_pwm4	pfe_uart_rx	dect3
AB20	gpio13	gpio13	tim_pwm5	pfe_uart_tx	dect4
F4	gpio14	gpio14	sata1_act_led	tim_evnt0	dect5
H4	gpio15	gpio15	sata1_cp_pod	tim_evnt1	rtcosc
AC21	i2c_scl	i2c_scl	gpio16	N/A	N/A
AB21	i2c_sda	i2c_sda	gpio17	N/A	N/A
AB22	spi_ss0_n	spi_ss0_n	gpio18	N/A	N/A
AE23	spi_ss1_n	spi_ss1_n	gpio19	N/A	N/A
B6	spi_2_ss1_n	spi_2_ss1_n	gpio20	N/A	N/A
AD23	spi_ss2_n	spi_ss2_n	gpio21	N/A	N/A
AA22	spi_ss3_n	spi_ss3_n	gpio22	N/A	N/A
AD11	exp_cs2_n	exp_cs2_n	gpio23	N/A	N/A
AE11	exp_cs3_n	exp_cs3_n	gpio24	N/A	N/A
AE12	exp_ale	exp_ale	gpio25	N/A	N/A
AD12	exp_rdy	exp_rdy	gpio26	N/A	N/A
Y23	tm_ext_reset	tm_ext_reset	gpio27	N/A	N/A
AC5	exp_nand_cs	exp_nand_cs	gpio28	N/A	N/A
AB5	exp_nand_rdy	exp_nand_rdy	gpio29	N/A	N/A
AE22	spi_txd	spi_txd	gpio30	N/A	N/A
AC22	spi_sclk	spi_sclk	gpio31	N/A	N/A
AD22	spi_rxd	spi_rxd	gpio32	N/A	N/A
D5	spi_2_rxd	spi_2_rxd	gpio33	N/A	N/A
A6	spi_2_ss0_n	spi_2_ss0_n	gpio34	N/A	N/A
AC8	exp_dq[8]	exp_dq[8]	gpio35	N/A	N/A
AD8	exp_dq[9]	exp_dq[9]	gpio36	N/A	N/A
AE8	exp_dq[10]	exp_dq[10]	gpio37	N/A	N/A
AB9	exp_dq[11]	exp_dq[11]	gpio38	N/A	N/A
AC9	exp_dq[12]	exp_dq[12]	gpio39	N/A	N/A
AD9	exp_dq[13]	exp_dq[13]	gpio40	N/A	N/A
AE9	exp_dq[14]	exp_dq[14]	gpio41	N/A	N/A
AC10	exp_dq[15]	exp_dq[15]	gpio42	N/A	N/A
AC12	exp_dm[1]	exp_dm[1]	gpio43	N/A	N/A
W19	coresight_d0	coresight_d0	gpio44	N/A	N/A
W18	coresight_d1	coresight_d1	gpio45	N/A	N/A
V19	coresight_d2	coresight_d2	gpio46	N/A	N/A
V18	coresight_d3	coresight_d3	gpio47	N/A	N/A
T18	coresight_d4	coresight_d4	gpio48	N/A	N/A
T19	coresight_d5	coresight_d5	gpio49	N/A	N/A
R18	coresight_d6	coresight_d6	gpio50	N/A	N/A
R19	coresight_d7	coresight_d7	gpio51	N/A	N/A
N18	coresight_d8	coresight_d8	gpio52	N/A	N/A
N19	coresight_d9	coresight_d9	gpio53	N/A	N/A
M18	coresight_d10	coresight_d10	gpio54	N/A	N/A
M19	coresight_d11	coresight_d11	gpio55	N/A	N/A
K19	coresight_d12	coresight_d12	gpio56	N/A	N/A
K18	coresight_d13	coresight_d13	gpio57	N/A	N/A
J19	coresight_d14	coresight_d14	gpio58	N/A	N/A
J18	coresight_d15	coresight_d15	gpio59	N/A	N/A
AE21	uart1_rx	uart1_rx	uart_s2_rx	N/A	N/A
AD21	uart1_tx	uart1_tx	uart_s2_tx	N/A	N/A
AC23	tdm_ck	tdm_ck	zsi_zclk	gpio63	isi_psclk
AD24	tdm_fs	tdm_fs	zsi_fsync	gpio62	gpio62 (slic_n_reset)
AC25	tdm_dr	tdm_dr	zsi_zmiso	gpio61	isi_data_i
AC24	tdm_dx	tdm_dx	zsi_zmosi	gpio60	isi_data_o

3.2. Registers

Base address	0x90470000
Size	0x00000?00

Interrupt source	GIC SPI interrupt
PTP0	0 (level)
PTP1	1 (level)
PTP2	2 (level)
PTP3	3 (level)
GPIO0	45 (level/edge)
GPIO1	46 (level/edge)
GPIO2	47 (level/edge)
GPIO3	48 (level/edge)
GPIO4	49 (level/edge)
GPIO5	50 (level/edge)
GPIO6	51 (level/edge)
GPIO7	52 (level/edge)

Wake-up source	PMU interrupt
GPIO0	0 (level/edge)
GPIO1	1 (level/edge)
GPIO2	2 (level/edge)
GPIO3	3 (level/edge)
GPIO4	4 (level/edge)
GPIO5	5 (level/edge)
GPIO6	6 (level/edge)
GPIO7	7 (level/edge)
TIMER0	8 (edge)
TIMER1	9 (edge)
TIMER2	10 (edge)
TIMER3	11 (edge)
ZDS/MSIF	12 (level)
RTC_ALM	13 (level/edge)
RTC_PRI	14 (level)
PCIe0	15 (level)
PCIe1	16 (level)
SATA	17 (level)
SATA_MSI	18 (level)
USB2p0	19 (level)
USB3p0	20 (level/edge)
HFE_0	21 (level)
WOL	22 (edge)
CSS	23 (level)
DUS_DMAC	24 (level)
DUS_UART0	25 (level)
DUS_UART1/UART_S2	26 (level)
HFE_1	27 (level)
USP3p0_PM	28 (level)
PTP0	29 (level)
PTP1	30 (level)
PTP2	31 (level)

Symbol	Offset	Description
GPIO_OUTPUT_REG	0x0000	Output value to apply to GPIOs 31-0
GPIO_OE_REG	0x0004	Direction configuration for GPIOs 31-0
GPIO_INT_CFG_REG	0x0008	Interrupt configuration for GPIOs 7-0
GPIO_ARM_UNALIGNED_LOGIC_ENABLE	0x000c
GPIO_INPUT_REG	0x0010	GPIOs 31-0 input values
GPIO_APB_WS	0x0014	APB bus wait states?
GPIO_SYSTEM_CONFIG	0x001c	Bootstrap pins configuration value
GPIO_MBIST	0x0020	Memory BIST?
GPIO_TDM_MUX	0x0028	TDM loopback config? FS output enable?
GPIO_ARM_ID	0x0030	Part number info (empty?)
GPIO_MISC_CTRL	0x0034	Misc pads and fabric remap control
GPIO_DDR_AXI_CTRL	0x0038
GPIO_DDRC_STATUS	0x003c
GPIO_BOOTSTRAP_STATUS	0x0040
GPIO_BOOTSTRAP_OVERRIDE	0x0044
GPIO_USB_PHY_BIST_STATUS_REG	0x0048
GPIO_GENERAL_CONTROL_REG	0x004c
GPIO_DEVICE_ID_REG	0x0050	C2000 revision info
GPIO_ARM_MEMORY_SENSE_AMP	0x0054
GPIO_PIN_SELECT_REG	0x0058	Pad function selection
GPIO_PIN_SELECT_REG2	0x005c	Pad function selection
GPIO_MISC_PIN_SELECT	0x0060	Misc pad function selection
GPIO_FABRIC_CTRL_REG	0x006c	Interconnect fabric configuration
GPIO_A9_AUTH_CTRL_REG	0x0070
GPIO_A9_ACP_CONF_REG	0x0074	Accelerator Coherency Port configuration
GPIO_PCIE_CLK_OUT_CTRL_REG	0x0080
GPIO_INTR_STAT_REG	0x0094	Interrupt status register. Used for PTP0-PTP3 (Processor-to-processor IRQs)
GPIO_INTR_CLR_REG	0x0098	Clear interrupt. Used for PTP0-PTP3 (Processor-to-processor IRQs)
GPIO_INTR_SET_REG	0x009c	Set interrupt. Used for PTP0-PTP3 (Processor-to-processor IRQs)
GPIO_INTR_MASK_REG	0x00a0
GPIO_CSS_DECT_SYS_CFG0	0x00b0
GPIO_CSS_DECT_SYS_CFG1	0x00b4
GPIO_CSS_DECT_CTRL	0x00b8
GPIO_63_32_PIN_OUTPUT	0x00d0	Output value to apply to GPIOs 63-32
GPIO_63_32_PIN_OUTPUT_EN	0x00d4	Direction configuration for GPIOs 63-32
GPIO_63_32_PIN_INPUT	0x00d8	GPIOs 63-32 input values
GPIO_63_32_PIN_SELECT	0x00dc	GPIOs 63-32 GPIO/function selection
GPIO_PAD_CONFIG0	0x0100	Pad configuration register
GPIO_PAD_CONFIG1	0x0104	Pad configuration register
GPIO_PAD_CONFIG2	0x0108	Pad configuration register
GPIO_PAD_CONFIG3	0x010c	Pad configuration register
GPIO_PAD_CONFIG4	0x0110	Pad configuration register
GPIO_PAD_CONFIG5	0x0114	Pad configuration register
GPIO_PAD_CONFIG6	0x0118	Pad configuration register
GPIO_PAD_CONFIG7	0x011c	Pad configuration register
GPIO_PAD_CONFIG8	0x0120	Pad configuration register
GPIO_PAD_CONFIG9	0x0124	Pad configuration register
GPIO_PAD_CONFIG10	0x0128	Pad configuration register
GPIO_PAD_CONFIG11	0x012c	Pad configuration register
GPIO_PAD_CONFIG12	0x0130	Pad configuration register
GPIO_PAD_CONFIG13	0x0134	Pad configuration register
GPIO_PAD_CONFIG14	0x0138	Pad configuration register
GPIO_PMU_INTR_STAT0	0x0150	PMU interrupt status (using MASK0)
GPIO_PMU_INTR_STAT1	0x0154	PMU interrupt status (using MASK1)
GPIO_PMU_INTR_STAT	0x015c	PMU interrupt status (ignoring MASK0/1)
GPIO_PMU_INTR_CLR	0x0160	PMU interrupt clear resiter
GPIO_PMU_INTR_SET	0x0164	PMU interrupt set register
GPIO_PMU_INTR_MASK0	0x0168	PMU interrupt mask 0 (PFE Util-PE?)
GPIO_PMU_INTR_MASK1	0x016c	PMU interrupt mask 1 (CSS?)
GPIO_MEM_EMA_CONFIG0	0x01a0	Memory EMA (Extra Margin Adjustment)
GPIO_MEM_EMA_CONFIG1	0x01a4	Memory EMA (Extra Margin Adjustment)
GPIO_MEM_EMA_CONFIG2	0x01a8	Memory EMA (Extra Margin Adjustment)
GPIO_MEM_EMA_CONFIG3	0x01ac	Memory EMA (Extra Margin Adjustment)
GPIO_MEM_EMA_CONFIG4	0x01b0	Memory EMA (Extra Margin Adjustment)
GPIO_MEM_EMA_CONFIG5	0x01b4	Memory EMA (Extra Margin Adjustment)
GPIO_MEM_EMA_CONFIG6	0x01b8	Memory EMA (Extra Margin Adjustment)

3.2.1. GPIO_OUTPUT_REG (0x90470000)

Allow to set a GPIO pin output value. GPIO must be configured as an output for the value in this register to have any effect.

Symbol	Bit range	R/W	Description
GPIO31	31	R/W	GPIO 31 output value. 0=low 1=high
GPIOxx	xx	R/W	GPIO xx output value. 0=low 1=high
GPIO0	0	R/W	GPIO 0 output value. 0=low 1=high

3.2.2. GPIO_OE_REG (0x90470004)

Configure a GPIO pin as input or output.

Symbol	Bit range	R/W	Description
GPIO31	31	R/W	GPIO 31 output enable. 0=input 1=output
GPIOxx	xx	R/W	GPIO xx output enable. 0=input 1=output
GPIO0	0	R/W	GPIO 0 output enable. 0=input 1=output

3.2.3. GPIO_INT_CFG_REG (0x90470008)

Configure GPIO input pins 0-7 behaviour as interrupt sources. The matching interrupts in the GIC are SPIs 45 through 52 (IDs 77 through 84).

For each of those GPIOs, the configuration value can be: 0 - Disable 1 - Falling edge 2 - Rising edge 3 - Active high (level-triggered)

Symbol	Bit range	R/W	Description
GPIO7	15-14	R/W	GPIO7 IRQ config
GPIO6	13-12	R/W	GPIO6 IRQ config
GPIO5	11-10	R/W	GPIO5 IRQ config
GPIO4	9-8	R/W	GPIO4 IRQ config
GPIO3	7-6	R/W	GPIO3 IRQ config
GPIO2	5-4	R/W	GPIO2 IRQ config
GPIO1	3-2	R/W	GPIO1 IRQ config
GPIO0	1-0	R/W	GPIO0 IRQ config

3.2.4. GPIO_INPUT_REG (0x90470010)

Allow to read a GPIO pin input value. For outputs, read value should be the same as the output value. For pins not configured as GPIO, the value may reflect the current logical state of the pin.

Symbol	Bit range	R/W	Description
GPIO31	31	R	GPIO 31 output value. 0=low 1=high
GPIOxx	xx	R	GPIO xx output value. 0=low 1=high
GPIO0	0	R	GPIO 0 output value. 0=low 1=high

3.2.5. GPIO_SYSTEM_CONFIG (0x9047001c)

System configuration bootstrap pins register.

The 26 lower bits are sampled from the expansion port 26 address lines on reset.

Bits 25-22 are undocumented, but some are used by the Internal Boot ROM (IBR).

Symbol	Bit range	R/W	Description
?	28	R	Unknown. Used by IBR.
?	25-24	R	Unknown. Used by IRB for NAND config. Valid values: 0-2. 3=invalid
?	23-22	R	Unknown. Used by IRB for NAND config.
CLOCK	21	R	Whether IBR should enable PLLs. 0: Keep disabled 1: Enable PLLs
SPI_SCLK_POL	20	R	SPI SCLK polarity. 0: -ve 1: +ve
EXT_ID_READ_SEL	19-17	R	Extended ID Read Select. Purpose unknown. Overlaps previous bits. Used by IBR for NAND config.
SPI_ADDR_LEN	19-18	R	0: N/A 1: 2 bytes 2: 3 bytes 3: 4 bytes (Fast SPI only supports 3-byte addresses)
SECURE_BOOT	17	R	0: Disable 1: Enable
FAST_UART_SPEED	16	R	0: 115200 bauds 1: 921600 bauds
CORESIGHT_DRV	15	R	0: Drive interface 1: Tri-state (if unused or used as GPIOs)
EXP_DM_DRV	14	R	EXP_DM driving mode - 0: bus is driven only during writes 1: bus is driven all the time
GEM2_CNF	13	R	GEM2 mode - 0: GEMAC (PPFE) 1: I2S/CSS
SERDES2_CNF	12	R	SerDes2 mode - 0: SATA1 1: SGMII
SERDES1_CNF	11	R	SerDes1 mode - 0: PCIe1 1: SATA0
L2CC_AXI_SYNC	10	R	0: L2CC and AXI clocks are asynchronous 1: L2CC and AXI clocks are synchronous and balanced
SYS_PLL_REF_CLK	9-8	R	0: USB XTAL (Officially reserved, but seen used in the wild) 1: SerDes0 refclk output (broken) 2: SerDes2 refclk output (broken) 3: SerDes XTAL
SERDES_OSC_FREQ	7	R	0: 48 MHz SerDes clock is used 1: 24 MHz SerDes clock is used
SERDES_OSC_XTAL	6	R	0: Crystal is connected to XI and XO 1: Clock is connected to XI
USB_OSC_FREQ	5	R	(Officially unused. In effect, should be the same as bit 7) 0: 48 MHz USB XTAL 1: 24 MHz USB XTAL
(none)	4	R	Reserved
TDM_CLK_OUT	3	R	0: TDM clock is driven by external device 1: TDM clock is driven by C2000
BOOT_OPT	2-0	R	Boot device (refer to the table below)

BOOT_OPT	Boot device
0	Low-speed SPI
1	I2C
2	High-speed SPI
3	UART
4	Reserved
5	SATA
6	8 bit NOR
7	16 bit NOR

3.2.6. GPIO_MISC_CTRL (0x90470034)

Misc pads and fabric remap control.

Symbol	Bit range	R/W	Description
GEM2_PAD_COMPENSATION	31-30	R/W	GEM2? TX pad compensation logic. Set to 0 in bootloader for 2.5V RGMII)
GEM2_?	29-28	R/W	Probably something related to GEM1 pads
GEM1_PAD_COMPENSATION	27-26	R/W	GEM1? TX pad compensation logic. Set to 0 in bootloader for 2.5V RGMII)
GEM1_?	25-24	R/W	Probably something related to GEM1 pads
GEM0_PAD_COMPENSATION	23-22	R/W	GEM0? TX pad compensation logic. Set to 0 in bootloader for 2.5V RGMII)
GEM0_?	21-20	R/W	Probably something related to GEM0 pads
GEM2_REFCLK_TRISTATE	16	R/W	Tri-state GEM2_REFCLK pad
GEM1_REFCLK_TRISTATE	15	R/W	Tri-state GEM1_REFCLK pad
GEM0_REFCLK_TRISTATE	14	R/W	Tri-state GEM0_REFCLK pad
EXP_CLK_TRISTATE	13	R/W	Tri-state EXP_CLK pad
DISABLE_FABRIC_REMAP	4	R/W	Disable IBR remap

3.2.7. GPIO_BOOTSTRAP_STATUS (0x90470040)

Bootstrap pins status register.

Essentially the same as GPIO_SYSTEM_CONFIG.

3.2.8. GPIO_BOOTSTRAP_OVERRIDE (0x90470044)

Bootstrap pins override register.

Used in bootloader for tests.

3.2.9. GPIO_DEVICE_ID_REG (0x90470050)

SoC revision info.

Symbol	Bit range	R/W	Description
C2K_REVISION	31-24	R	C2000 SoC revision. 0=A0, 1=A1

3.2.10. GPIO_PIN_SELECT_REG (0x90470058)

Pins 0-15 function selection register.

Symbol	Bit range	R/W	Description
GPIO15	31-30	R/W	GPIO pin 15 function: 0=GPIO 1=SATA1_CP_POD 2=TIM_EVENT1 3=RTCOSC
GPIO14	29-28	R/W	GPIO pin 14 function: 0=GPIO 1=SATA1_ACT_LED 2=TIM_EVENT0 3=DECT5
GPIO13	27-26	R/W	GPIO pin 13 function: 0=GPIO 1=PWM5 2=PFE_UART_TX 3=DECT4
GPIO12	25-24	R/W	GPIO pin 12 function: 0=GPIO 1=PWM4 2=PFE_UART_RX 3=DECT3
GPIO11	23-22	R/W	GPIO pin 11 function: 0=GPIO 1=unknown/reserved 2=UART0_CTS_N 3=DECT2
GPIO10	21-20	R/W	GPIO pin 10 function: 0=GPIO 1=unknown/reserved 2=UART0_RTS_N 3=DECT0
GPIO9	19-18	R/W	GPIO pin 9 function: 0=GPIO 1=unknown/reserved 2=UART0_TX 3=unknown/reserved
GPIO8	17-16	R/W	GPIO pin 8 function: 0=GPIO 1=unknown/reserved 2=UART0_RX 3=unknown/reserved
GPIO7	15-14	R/W	GPIO pin 7 function: 0=GPIO 1=PWM3 2=SATA0_CP_POD 3=unknown/reserved
GPIO6	13-12	R/W	GPIO pin 6 function: 0=GPIO 1=PWM2 2=SATA0_ACT_LED 3=unknown/reserved
GPIO5	11-10	R/W	GPIO pin 5 function: 0=GPIO 1=PWM1 2-3=unknown/reserved
GPIO4	9-8	R/W	GPIO pin 4 function: 0=GPIO 1=PWM0 2-3=unknown/reserved
GPIO3	7-6	R/W	GPIO pin 3 function: 0=GPIO 1-3=unknown/reserved
GPIO2	5-4	R/W	GPIO pin 2 function: 0=GPIO 1-3=unknown/reserved
GPIO1	3-2	R/W	GPIO pin 1 function: 0=GPIO 1-3=unknown/reserved
GPIO0	1-0	R/W	GPIO pin 0 function: 0=GPIO 1-3=unknown/reserved

3.2.11. GPIO_PIN_SELECT_REG2 (0x9047005c)

Pins 16-31 function selection register.

Symbol	Bit range	R/W	Description
GPIO31	31-30	R/W	GPIO pin 31 function: 0=SPI_SCLK 1=GPIO 2-3=unknown/reserved
GPIO30	29-28	R/W	GPIO pin 30 function: 0=SPI_TXD 1=GPIO 2-3=unknown/reserved
GPIO29	27-26	R/W	GPIO pin 29 function: 0=EXP_NAND_RDY 1=GPIO 2-3=unknown/reserved
GPIO28	25-24	R/W	GPIO pin 28 function: 0=EXP_NAND_CS 1=GPIO 2-3=unknown/reserved
GPIO27	23-22	R/W	GPIO pin 27 function: 0=TM_EXT_RESET 1=GPIO 2-3=unknown/reserved
GPIO26	21-20	R/W	GPIO pin 26 function: 0=EXP_RDY 1=GPIO 2-3=unknown/reserved
GPIO25	19-18	R/W	GPIO pin 25 function: 0=EXP_ALE 1=GPIO 2-3=unknown/reserved
GPIO24	17-16	R/W	GPIO pin 24 function: 0=EXP_CS3_N 1=GPIO 2-3=unknown/reserved
GPIO23	15-14	R/W	GPIO pin 23 function: 0=EXP_CS2_N 1=GPIO 2-3=unknown/reserved
GPIO22	13-12	R/W	GPIO pin 22 function: 0=SPI_SS3_N 1=GPIO 2-3=unknown/reserved
GPIO21	11-10	R/W	GPIO pin 21 function: 0=SPI_SS2_N 1=GPIO 2-3=unknown/reserved
GPIO20	9-8	R/W	GPIO pin 20 function: 0=SPI_2_SS1_N 1=GPIO 2-3=unknown/reserved
GPIO19	7-6	R/W	GPIO pin 19 function: 0=SPI_SS1_N 1=GPIO 2-3=unknown/reserved
GPIO18	5-4	R/W	GPIO pin 18 function: 0=SPI_SS0_N 1=GPIO 2-3=unknown/reserved
GPIO17	3-2	R/W	GPIO pin 17 function: 0=I2C_SDA 1=GPIO 2-3=unknown/reserved
GPIO16	1-0	R/W	GPIO pin 16 function: 0=I2C_SCL 1=GPIO 2-3=unknown/reserved

3.2.12. GPIO_MISC_PIN_SELECT (0x90470060)

Misc pin selection (i.e. not GPIOs) register

Symbol	Bit range	R/W	Description
DDRC_ODT_SRC	7-6	R/W	DDRC ODT (on-die termination) source select? Set to 1 in bootloader
TDM_MUX	5-4	R/W	TDM interface mux. 0=TDM (SiLabs si3227) 1=ZDS (Zarlink le88264) 2=GPIOs 60-63 3=MSIF (SiLabs si32268)
UART1_MUX	1-0	R/W	UART1/2 selection. 0=UART1 1=UART2 (slow/legacy UART)? 2=? 3=?

3.2.13. GPIO_FABRIC_CTRL_REG (0x9047006c)

Symbol	Bit range	R/W	Description
?	8-2	R/W	Unknown
SATA_DDRC_PORT	1-0	R/W	DDRC port used for SATA controller. Set to 2 in Linux.

3.2.14. GPIO_CSS_DECT_SYS_CFG0 (0x904700b0)

CSS/DECT/ARM926 PMU registers.

Symbol	Bit range	R/W	Description
BMP_RESET	14	R/W
GDMAC_RESET	13	R/W	DMA controller reset. 0=running 1=in reset
TIMERS_RESET	12	R/W	Timers reset. 0=running 1=in reset
ARM_MAIN_RESET	11	R/W	ARM926 reset. 0=running 1=in reset
CSS_MAIN_RESET	10	R/W	CSS block reset. 0=running 1=in reset
BMP_OSC_CLOCK_ENABLE	7	R/W
BMP_HCLK_CLOCK_ENABLE	6	R/W
GDMAC_PCLK_CLOCK_ENABLE	5	R/W	DMA controller APB clock enable. 0=disabled 1=enabled
GDMAC_HCLK_CLOCK_ENABLE	4	R/W	DMA controller AHB clock enable. 0=disabled 1=enabled
TIMER2_CLOCK_ENABLE	3	R/W	Timer2 clock enable. 0=disabled 1=enabled
TIMER1_CLOCK_ENABLE	2	R/W	Timer1 clock enable. 0=disabled 1=enabled
ARM_CLOCK_ENABLE	1	R/W	ARM926 clock enable. 0=disabled 1=enabled
CSS_MAIN_CLOCK_ENABLE	0	R/W	CSS block clock enable. 0=disabled 1=enabled

3.2.15. GPIO_CSS_DECT_SYS_CFG1 (0x904700b4)

Symbol	Bit range	R/W	Description
BCLK_CLOCK_ENABLE	16	R/W

3.2.16. GPIO_CSS_DECT_CTRL (0x904700b8)

Symbol	Bit range	R/W	Description
RF_RESET	16	R/W
?	15-0	R/W	DECT slave interface remap settings. Should be set to 0x3808.

3.2.17. GPIO_63_32_PIN_OUTPUT (0x904700d0)

Set the output values for GPIOs 32-63. For pins configured as output, setting the bit drives the pin high, clearing it drives the pin low. For pins configured as input, setting the bit has no effect.

Symbol	Bit range	R/W	Description
GPIO63	31	R/W	GPIO 63 output value. For output: 0=low 1=high
GPIOxx	(xx - 32)	R/W	GPIO xx output value. For output: 0=low 1=high
GPIO32	0	R/W	GPIO 32 output value. For output: 0=low 1=high

3.2.18. GPIO_63_32_PIN_OUTPUT_EN (0x904700d4)

Configure GPIOs 32-63 as inputs or outputs.

Beware, value is inverted wrt. GPIO_OE_REG.

Symbol	Bit range	R/W	Description
GPIO63	31	R/W	GPIO 63 input/output config. 0=output 1=input
GPIOxx	(xx - 32)	R/W	GPIO xx input/output config. 0=output 1=input
GPIO32	0	R/W	GPIO 32 input/output config. 0=output 1=input

3.2.19. GPIO_63_32_PIN_INPUT (0x904700d8)

Read input values for GPIOs 32-63. Can also read pin value even if pin is not configured as a GPIO, or if configured as a GPIO output.

Symbol	Bit range	R/W	Description
GPIO63	31	R	GPIO 63 input value. 0=low 1=high
GPIOxx	xx-32	R	GPIO xx input value. 0=low 1=high
GPIO32	0	R	GPIO 32 input value. 0=low 1=high

3.2.20. GPIO_63_32_PIN_SELECT (0x904700dc)

Select function for GPIOs 32-63.

Symbol	Bit range	R/W	Description
GPIO63	31	R/W	GPIO 63 function. 0=selected by TDM_MUX in GPIO_MISC_PIN_SELECT 1=unknown/reserved
GPIO62	30	R/W	GPIO 62 function. 0=selected by TDM_MUX in GPIO_MISC_PIN_SELECT 1=unknown/reserved
GPIO61	29	R/W	GPIO 61 function. 0=selected by TDM_MUX in GPIO_MISC_PIN_SELECT 1=unknown/reserved
GPIO60	28	R/W	GPIO 60 function. 0=selected by TDM_MUX in GPIO_MISC_PIN_SELECT 1=unknown/reserved
GPIO59	27	R/W	GPIO 59 function. 0=CORESIGHT_D15 1=GPIO
GPIO58	26	R/W	GPIO 58 function. 0=CORESIGHT_D14 1=GPIO
GPIO57	25	R/W	GPIO 57 function. 0=CORESIGHT_D13 1=GPIO
GPIO56	24	R/W	GPIO 56 function. 0=CORESIGHT_D12 1=GPIO
GPIO55	23	R/W	GPIO 55 function. 0=CORESIGHT_D11 1=GPIO
GPIO54	22	R/W	GPIO 54 function. 0=CORESIGHT_D10 1=GPIO
GPIO53	21	R/W	GPIO 53 function. 0=CORESIGHT_D9 1=GPIO
GPIO52	20	R/W	GPIO 52 function. 0=CORESIGHT_D8 1=GPIO
GPIO51	19	R/W	GPIO 51 function. 0=CORESIGHT_D7 1=GPIO
GPIO50	18	R/W	GPIO 50 function. 0=CORESIGHT_D6 1=GPIO
GPIO49	17	R/W	GPIO 49 function. 0=CORESIGHT_D5 1=GPIO
GPIO48	16	R/W	GPIO 48 function. 0=CORESIGHT_D4 1=GPIO
GPIO47	15	R/W	GPIO 47 function. 0=CORESIGHT_D3 1=GPIO
GPIO46	14	R/W	GPIO 46 function. 0=CORESIGHT_D2 1=GPIO
GPIO45	13	R/W	GPIO 45 function. 0=CORESIGHT_D1 1=GPIO
GPIO44	12	R/W	GPIO 44 function. 0=CORESIGHT_D0 1=GPIO
GPIO43	11	R/W	GPIO 43 function. 0=EXP_DM[1] 1=GPIO
GPIO42	10	R/W	GPIO 42 function. 0=EXP_DQ[15] 1=GPIO
GPIO41	9	R/W	GPIO 41 function. 0=EXP_DQ[14] 1=GPIO
GPIO40	8	R/W	GPIO 40 function. 0=EXP_DQ[13] 1=GPIO
GPIO39	7	R/W	GPIO 39 function. 0=EXP_DQ[12] 1=GPIO
GPIO38	6	R/W	GPIO 38 function. 0=EXP_DQ[11] 1=GPIO
GPIO37	5	R/W	GPIO 37 function. 0=EXP_DQ[10] 1=GPIO
GPIO36	4	R/W	GPIO 36 function. 0=EXP_DQ[9] 1=GPIO
GPIO35	3	R/W	GPIO 35 function. 0=EXP_DQ[8] 1=GPIO
GPIO34	2	R/W	GPIO 34 function. 0=SPI_2_SS0_N 1=GPIO
GPIO33	1	R/W	GPIO 33 function. 0=SPI_2_RXD 1=GPIO
GPIO32	0	R/W	GPIO 32 function. 0=SPI_RXD 1=GPIO

3.2.21. GPIO_PAD_CONFIGx (0x90470100 + x*4)

Symbol	Bit range	R/W	Description
X_4_SLEW_RATE	29	R/W	Pad output slew rate. 0=slow 1=fast
X_4_SCHMITT_TRIGGER?	28	R/W	Enable Schmitt trigger on input. 0=disable 1=enable
X_4_PULL_EN	27	R/W	Enable internal weak pull up/down resistor
X_4_PULL_SEL	26	R/W	Pull-up/down resistor selection. 0=pull-down 1=pull-up
X_4_DRIVE_STRENGTH	25-24	R/W	Drive strength. 0=x1 1=x3 2=x2 3=x4
X_3_SLEW_RATE	23	R/W	Pad output slew rate. 0=slow 1=fast
X_3_SCHMITT_TRIGGER?	22	R/W	Enable Schmitt trigger on input. 0=disable 1=enable
X_3_PULL_EN	21	R/W	Enable internal weak pull up/down resistor
X_3_PULL_SEL	20	R/W	Pull-up/down resistor selection. 0=pull-down 1=pull-up
X_3_DRIVE_STRENGTH	19-18	R/W	Drive strength. 0=x1 1=x3 2=x2 3=x4
X_2_SLEW_RATE	17	R/W	Pad output slew rate. 0=slow 1=fast
X_2_SCHMITT_TRIGGER?	16	R/W	Enable Schmitt trigger on input. 0=disable 1=enable
X_2_PULL_EN	15	R/W	Enable internal weak pull up/down resistor
X_2_PULL_SEL	14	R/W	Pull-up/down resistor selection. 0=pull-down 1=pull-up
X_2_DRIVE_STRENGTH	13-12	R/W	Drive strength. 0=x1 1=x3 2=x2 3=x4
X_1_SLEW_RATE	11	R/W	Pad output slew rate. 0=slow 1=fast
X_1_SCHMITT_TRIGGER?	10	R/W	Enable Schmitt trigger on input. 0=disable 1=enable
X_1_PULL_EN	9	R/W	Enable internal weak pull up/down resistor
X_1_PULL_SEL	8	R/W	Pull-up/down resistor selection. 0=pull-down 1=pull-up
X_1_DRIVE_STRENGTH	7-6	R/W	Drive strength. 0=x1 1=x3 2=x2 3=x4
X_0_SLEW_RATE	5	R/W	Pad output slew rate. 0=slow 1=fast
X_0_SCHMITT_TRIGGER?	4	R/W	Enable Schmitt trigger on input. 0=disable 1=enable
X_0_PULL_EN	3	R/W	Enable internal weak pull up/down resistor
X_0_PULL_SEL	2	R/W	Pull-up/down resistor selection. 0=pull-down 1=pull-up
X_0_DRIVE_STRENGTH	1-0	R/W	Drive strength. 0=x1 1=x3 2=x2 3=x4

3.2.22. GPIO_PAD_CONFIG0 (0x90470100)

Symbol	Bit range	R/W	Description
TDM_DR_PULL_EN	27	R/W	TDM_DR pin bias enable. 0=no bias 1=pull-up/down
TDM_DR_PULL_SEL	26	R/W	TDM_DR pin pull-up/down selection. 0=pull-down 1=pull-up
TDM_DR_DRIVE_STRENGTH	25-24	R/W	TDM_DR drive strength. Set in Linux BSP. 0=x1 1=x3 2=x2 3=x4
TDM_DX_PULL_EN	21	R/W	TDM_DX pin bias enable. 0=no bias 1=pull-up/down
TDM_DX_PULL_SEL	20	R/W	TDM_DX pin pull-up/down selection. 0=pull-down 1=pull-up
TDM_DX_DRIVE_STRENGTH	19-18	R/W	TDM_DX drive strength. Set in Linux BSP. 0=x1 1=x3 2=x2 3=x4
TDM_FS_PULL_EN	15	R/W	TDM_FS pin bias enable. 0=no bias 1=pull-up/down
TDM_FS_PULL_SEL	14	R/W	TDM_FS pin pull-up/down selection. 0=pull-down 1=pull-up
TDM_FS_DRIVE_STRENGTH	13-12	R/W	TDM_FS drive strength. Set in Linux BSP. 0=x1 1=x3 2=x2 3=x4
TDM_CK_PULL_EN	9	R/W	TDM_CK pin bias enable. 0=no bias 1=pull-up/down
TDM_CK_PULL_SEL	8	R/W	TDM_CK pin pull-up/down selection. 0=pull-down 1=pull-up
TDM_CK_DRIVE_STRENGTH	7-6	R/W	TDM_CK drive strength. Set in Linux BSP. 0=x1 1=x3 2=x2 3=x4

3.2.23. GPIO_PAD_CONFIG1 (0x90470104)

Symbol	Bit range	R/W	Description
SPI_RXD_PULL_EN	3	R/W	Pull-up/down enable for SPI_RXD pad. 0=disable 1=enable
SPI_RXD_PULL_SEL	2	R/W	Pull-up/down selection for SPI_RXD pad. 0=pull-down 1=pull-up\|
SPI_RXD_DRIVE_STRENGTH?	1-0	R/W	Drive strength. 0=x1 1=x3 2=x2 3=x4

3.2.24. GPIO_PAD_CONFIG2 (0x90470108)

Symbol	Bit range	R/W	Description
SPI_2_SS0_N_SLEW_RATE?	17	R/W	Pad output slew rate. 0=slow 1=fast
SPI_2_SS0_N_PULL_SEL	14	R/W	Enable pull-up resistor on SPI_2_SS0_N pad
SPI_2_SS0_N_DRIVE_STRENGTH?	13-12	R/W	Drive strength. 0=x1 1=x3 2=x2 3=x4
SPI_2_RXD_PULL_EN	3	R/W	Pull-up/down enable for SPI_2_RXD pad. 0=disable 1=enable
SPI_2_RXD_PULL_SEL	2	R/W	Pull-up/down selection for SPI_2_RXD pad. 0=pull-down 1=pull-up\|
SPI_2_RXD_DRIVE_STRENGTH?	1-0	R/W	Drive strength. 0=x1 1=x3 2=x2 3=x4

3.2.25. GPIO_PAD_CONFIG3 (0x9047010c)

Symbol	Bit range	R/W	Description
GEM0_RXC_PULLDOWN?	20	R/W	Enable pull-down? resistor on GEM0_RXC pad
GEM0_RXC_DRIVE_STRENGTH?	19-18	R/W	GEM0 RXC drive strength?
GEM0_?_SLEW_RATE	17	R/W	GEM0 Tx ? slew rate
GEM0_?_DRIVE_STRENGTH	13-12	R/W	GEM0 ? drive strength. Set in bootloader. 2 for 3.3V RMII/RGMII, 3 for 2.5V RMII/RGMII
GEM0_?_SLEW_RATE	11	R/W	GEM0 Tx ? slew rate
GEM0_?_DRIVE_STRENGTH	7-6	R/W	GEM0 ? drive strength. Set in bootloader. 2 for 3.3V RMII/RGMII, 3 for 2.5V RMII/RGMII

3.2.26. GPIO_PAD_CONFIG4 (0x90470110)

Symbol	Bit range	R/W	Description
GEM1_RXC_PULLDOWN?	20	R/W	Enable pull-down? resistor on GEM1_RXC pad
GEM1_?_SLEW_RATE	17	R/W	GEM1 Tx ? slew rate
GEM1_?_DRIVE_STRENGTH	13-12	R/W	GEM1 ? drive strength. Set in bootloader. 2 for 3.3V RMII/RGMII, 3 for 2.5V RMII/RGMII
GEM1_?_SLEW_RATE	11	R/W	GEM1 Tx ? slew rate
GEM1_?_DRIVE_STRENGTH	7-6	R/W	GEM1 ? drive strength. Set in bootloader. 2 for 3.3V RMII/RGMII, 3 for 2.5V RMII/RGMII

3.2.27. GPIO_PAD_CONFIG5 (0x90470114)

Symbol	Bit range	R/W	Description
GEM2_RXC_PULLDOWN?	20	R/W	Enable pull-down? resistor on GEM2_RXC pad
GEM2_?_SLEW_RATE	17	R/W	GEM2 Tx ? slew rate
GEM2_?_DRIVE_STRENGTH	13-12	R/W	GEM2 ? drive strength. Set in bootloader. 2 for 3.3V RMII/RGMII, 3 for 2.5V RMII/RGMII
GEM2_?_SLEW_RATE	11	R/W	GEM2 Tx ? slew rate
GEM2_?_DRIVE_STRENGTH	7-6	R/W	GEM2 ? drive strength. Set in bootloader. 2 for 3.3V RMII/RGMII, 3 for 2.5V RMII/RGMII

3.2.28. GPIO_PAD_CONFIG6 (0x90470118)

Symbol	Bit range	R/W	Description
CORESIGHT_PULL_EN	21	R/W	Pull-up/down enable for CORESIGHT pads. 0=disable 1=enable
CORESIGHT_PULL_SEL	20	R/W	Pull-up/down selection for CORESIGHT pads. 0=pull-down 1=pull-up\|
CORESIGHT_DRIVE_STRENGTH?	19-18	R/W	Drive strength. 0=x1 1=x3 2=x2 3=x4

3.2.29. GPIO_PMU_INTR_SET (0x90470164)

Symbol	Bit range	R/W	Description
GPIO0_IRQ	0	R/W	Write 1 to set GPIO0 IRQ

4. SPI controller

The Comcerto 2000 features two SPI master controllers: a high speed and a low speed one. Both controllers are instances of the Synopsys Designware SPI master controller core.

Common features:

Master-only
Data frame size: 4 to 16 bits
Hardware and/or software slave select

HS SPI specific features:

Clock rate up to 50 MHz
2 hardware slave select outputs
FIFO depth: 32 words
Can be controlled by the DUSI DMA unit

LS SPI specific features:

Clock rate up to 14 MHz (16 MHz theoretical)
4 hardware slave select outputs
FIFO depth: 8 words
No DMA support

Remark: While the register documentation describes registers and fields for operating the SPI controller in slave mode, it does not mean that the C2000 actually implements them.

4.1. Registers

	HS SPI (DUSI)	LS SPI
Base address	0x96500000	0x90498000
Size	0x1000	0x1000
GIC SPI interrupt	28 (level)	29 (level)

Symbol	Offset	Description
CTRL0	0x00	SPI control register 0
CTRL1	0x04	SPI control register 1
SSIENR	0x08	Synchronous serial interface enable register
MWCR	0x0c	Microwire control register?
SER	0x10	Slave enable register
BAUDR	0x14	Baud rate divider register
TXFLTR	0x18	Tx FIFO level threshold register
RXFLTR	0x1c	Rx FIFO level threshold register
TXFLR	0x20	Tx FIFO level register
RXFLR	0x24	Rx FIFO level register
SR	0x28	Status register
IMR	0x2c	Interrupt mask register
ISR	0x30	Interrupt status register
RISR	0x34	Raw interrupt status register
TXOICR	0x38	Tx FIFO overflow interrupt clear register
RXOICR	0x3c	Rx FIFO overflow interrupt clear register
RXUICR	0x40	Rx FIFO underflow interrupt clear register
MSTICR	0x44	Multi master interrupt clear register
ICR	0x48	Interrupt clear register
DMACR	0x4c	DMA control register
DMATDLR	0x50	DMA Tx data level register
DMARDLR	0x54	DMA Rx data level register
IDR	0x58	ID register
VERSION	0x5c	Version register
DR	0x60	Data register
RXDLY	0xf0	Rx sample delay register

4.1.1. CTRL0 (HS: 0x96500000 LS: 0x90498000)

SPI control register 0

Symbol	Bit range	R/W	Description
CFS	15-12	RW	Control frame size. Selects the length of the control word for the Microwire frame format.
SRL	11	RW	Shift register loop. Connects the Tx shift register output to the Rx shift register input. 0=normal 1=loopback
SLVOE	10	RW	Slave output enable. No use in master mode.
TMOD	9-8	RW	Transmission mode. 0=Tx+Rx 1=Tx only 2=Rx only 3=EEPROM read
SCOL	7	RW	SPI clock polarity. 0=normal clock polarity (active high) 1=inverted clock polarity (active low)
SCPH	6	RW	SPI clock phase. 0=normal clock phase (serial clock toggles in the middle of the data bit) 1=inverted clock phase (serial clock toggles at the start of a data bit)
FRF	5-4	RW	Frame format. 0=SPI 1=SSP 2=Microwire 3=reserved
DFS	3-0	RW	Data frame size. Data frame size (in bits) = DFS + 1. Min frame size: 4 bits. Max frame size: 16 bits.

4.1.2. CTRL1 (HS: 0x96500004 LS: 0x90498004)

SPI control register 1

Symbol	Bit range	R/W	Description
NDF	15-0	RW	In receive-only or EEPROM modes, number of data frames to read. 0x0fff appears to be the maximum acceptable value.

4.1.3. SSIENR (HS: 0x96500008 LS: 0x90498008)

Synchronous serial interface enable register

Symbol	Bit range	R/W	Description
SSIEN	0	RW	Enable SPI controller. When disabled, transfers are stopped and FIFOs are cleared.

4.1.4. MWCR (HS: 0x9650000c LS: 0x9049800c)

Microwire control register?

Symbol	Bit range	R/W	Description

4.1.5. SER (HS: 0x96500010 LS: 0x90498010)

Slave enable register. When a bit in this register is set, the corresponding slave select line is activated when a serial transfer begins. Setting or clearing bits have no effect on the slave select lines until a transfer is started.

Also, all the slave select lines are deasserted when a transfer ends, which in Tx-only and Tx/Rx modes, happens when the Tx FIFO is empty (at least for non-DMA transfers). If the CPU and OS cannot keep up and write new data after the Tx FIFO has become empty, the slave select line will be deasserted, activated again and the new data written, which is usually not what you want.

Symbol	Bit range	R/W	Description
SE15	15	RW	Enable slave select line 15
SEx	x	RW	Enable slave select line x
SE0	0	RW	Enable slave select line 0

4.1.6. BAUDR (HS: 0x96500014 LS: 0x90498014)

Baud clock divider register

Symbol	Bit range	R/W	Description
SCDIV	15-0	RW	Serial clock divider. SCLK = DUSI_CLK / SCDIV. SCDIV must be even, between 2 and 0xfffe. Setting to 0 disables the clock.

4.1.7. TXFLTR (HS: 0x96500018 LS: 0x90498018)

Tx FIFO level threshold register.

Symbol	Bit range	R/W	Description
TXFLT	7-0	RW	Tx FIFO threshold at/below which an interrupt is generated. Max value depends on the FIFO size instantiated at design time.

4.1.8. RXFLTR (HS: 0x9650001c LS: 0x9049801c)

Rx FIFO level threshold register.

Symbol	Bit range	R/W	Description
RXFLT	7-0	RW	Rx FIFO threshold above which an interrupt is generated. Max value depends on the FIFO size instantiated at design time.

4.1.9. TXFLR (HS: 0x96500020 LS: 0x90498020)

Current Tx FIFO level register.

Symbol	Bit range	R/W	Description
TXFL	7-0	RO	Current Tx FIFO level. In Rx/Tx and Tx-only modes, transfer ends when FIFO level drops to 0.

4.1.10. RXFLR (HS: 0x96500024 LS: 0x90498024)

Current Rx FIFO level register.

Symbol	Bit range	R/W	Description
RXFL	7-0	RO	Current Rx FIFO level

4.1.11. SR (HS: 0x96500028 LS: 0x90498028)

Status register.

Symbol	Bit range	R/W	Description
DCOL	6	RO	Data collision error. Only relevant for controllers supporting multi-master operation (unsupported).
TX_ERR	5	RO	Tx error. Only relevant in slave operation (unsupported).
RF_FULL	4	RO	Rx FIFO full
RF_NOT_EMPT	3	RO	Rx FIFO not empty
TF_EMPT	2	RO	Tx FIFO empty
TF_NOT_FULL	1	RO	Tx FIFO not full
BUSY	0	RO	SSI busy flag, serial transfer in progress

4.1.12. IMR (HS: 0x9650002c LS: 0x9049802c)

Interrupt mask register.

Symbol	Bit range	R/W	Description
MSTIM	5	RW	Multi-Master contention interrupt
RXFIM	4	RW	Rx FIFO full interrupt
RXOIM	3	RW	Rx FIFO overflow interrupt
RXUIM	2	RW	Rx FIFO underflow interrupt
TXOIM	1	RW	Tx FIFO overflow interrupt
TXEIM	0	RW	Tx FIFO empty interrupt

4.1.13. ISR (HS: 0x96500030 LS: 0x90498030)

Interrupt status register (after the mask is applied).

Symbol	Bit range	R/W	Description
MSTIS	5	R	Multi-Master contention interrupt
RXFIS	4	R	Rx FIFO full interrupt
RXOIS	3	R	Rx FIFO overflow interrupt
RXUIS	2	R	Rx FIFO underflow interrupt
TXOIS	1	R	Tx FIFO overflow interrupt
TXEIS	0	R	Tx FIFO empty interrupt

4.1.14. RISR (HS: 0x96500034 LS: 0x90498034)

Raw interrupt status register (before the mask is applied).

Symbol	Bit range	R/W	Description
MSTIR	5	R	Multi-Master contention interrupt
RXFIR	4	R	Rx FIFO full interrupt
RXOIR	3	R	Rx FIFO overflow interrupt
RXUIR	2	R	Rx FIFO underflow interrupt
TXOIR	1	R	Tx FIFO overflow interrupt
TXEIR	0	R	Tx FIFO empty interrupt

4.1.15. TXOICR (HS: 0x96500038 LS: 0x90498038)

SPI Tx FIFO overflow interrupt clear register

Symbol	Bit range	R/W	Description
TXOICR	0	R	Clear transmit FIFO overflow interrupt. Read value reflects the interrupt status before clearing.

4.1.16. RXOICR (HS: 0x9650003c LS: 0x9049803c)

SPI Rx FIFO overflow interrupt clear register

Symbol	Bit range	R/W	Description
RXOICR	0	R	Clear receive FIFO overflow interrupt. Read value reflects the interrupt status before clearing.

4.1.17. RXUICR (HS: 0x96500040 LS: 0x90498040)

SPI Rx FIFO underflow interrupt clear register

Symbol	Bit range	R/W	Description
RXUICR	0	R	Clear receive FIFO underflow interrupt. Read value reflects the interrupt status before clearing.

4.1.18. MSTICR (HS: 0x96500044 LS: 0x90498044)

SPI multi-master interrupt clear register

Symbol	Bit range	R/W	Description
MSTICR	0	R	Clear multi-master contention interrupt. Read value reflects the interrupt status before clearing.

4.1.19. ICR (HS: 0x96500048 LS: 0x90498048)

Interrupt clear register. Reading this register will clear all pending interrupts.

Use this to clear overflow/underflow conditions.

The value returned when reading this register is unknown.

Symbol	Bit range	R/W	Description
ICR	0	R	Clear Tx overflow, Rx underflow, Rx overflow and multi-master interrupts when read.

4.1.20. DMACR (HS: 0x9650004c LS: 0x9049804c)

DMA control register.

Symbol	Bit range	R/W	Description
TDMAE	1	RW	Tx FIFO DMA channel enable
RDMAE	0	RW	Rx FIFO DMA channel enable

4.1.21. DMATDLR (HS: 0x96500050 LS: 0x90498050)

DMA Tx data level register.

Seen value: 0x10

Symbol	Bit range	R/W	Description
DMATDL	4-0	RW	Transmit data level at/below which a DMA request is made to fill the Tx FIFO. Writing a value equal or higher than the FIFO size will have no effect, and the register will retain its previous value.

4.1.22. DMARDLR (HS: 0x96500054 LS: 0x90498054)

DMA Rx data level register.

Seen value: 0x0f

Symbol	Bit range	R/W	Description
DMARDL	4-0	RW	Receive data level above which a DMA request is made to empty the Rx FIFO. Writing a value equal or higher than the FIFO size will have no effect, and the register will retain its previous value.

4.1.23. IDR (HS: 0x96500058 LS: 0x90498058)

ID register

Symbol	Bit range	R/W	Description
ID	31-0	R	ID value. Meaning unknown.

4.1.24. VERSION (HS: 0x9650005c LS: 0x9049805c)

SSI core version register?

Value for HS SPI: 0x3331352A "315*"
Value for LS SPI: 0x3330312A "301*"

Symbol	Bit range	R/W	Description
VER	31-0	R	SSI core revision number

4.1.25. DR (HS: 0x96500060 LS: 0x90498060)

Data register.

Registers in range 0x64-0xef are all aliases of DR in order to facilitate AHB burst transfers. Reading or writing in that range will have the same effect as accessing DR.

Symbol	Bit range	R/W	Description
DR	15-0	RW	Data register. When written, data word is pushed into the Tx FIFO. When reading, data is popped from the Rx FIFO. Written data must be right-justified. Read data is automatically right-justified.

4.1.26. RXDLY (HS: 0x965000f0 LS: 0x904980f0)

SPI sample delay register.

Symbol	Bit range	R/W	Description
RSD	15-0	RW	Rx data sample delay. Delay the sampling of the rxd signal by RSD DUSI_CLK cycles. A value higher than the depth of the internal shift register (4?) will cause a value a 0 to be used instead.

5. I2C controller

The Comcerto 2000 features an I2C controller supporting master and slave operation.

Features:

Multi-master support, with collision detection
7 of 10 bit addressing
General call address detection in slave mode
Supports repeated start condition

The controller supports 3 speeds ratings:

Low speed: 100 KHz
Full speed: 400 KHz
High speed: 3.4 MHz

The maximum speed must be selected to accomodate the slowest device on the bus.

This controller is based on the same IP as the one used in the Allwinner A64.

5.1. Registers

Base address	0x9049c000
Size	0x00000020

Interrupt source	GIC SPI interrupt
I2C	30 (level)

Symbol	Offset	Description
ADDR	0x00
DATA	0x04
CNTR	0x08
STAT	0x0c
CCRFS	0x0c
XADDR	0x10
CCRH	0x14
RESET	0x1c

5.1.1. ADDR (0x9049c000)

Own address of the I2C controller in slave mode.

Symbol	Bit range	R/W	Description
SLA	7-1	RW	Slave address. For 7-bit addressing: SLA is the 7-bit address. For 10-bit addressing: SLA is 11110b followed by the 2 most significant bits of the 10-bit address. The lower 8 bits are in the register XADDR.
GCE	0	RW	General call address enable (slave mode). 0: disabled 1: enabled

5.1.2. DATA (0x9049c004)

Data register for transmit and receive operations.

Symbol	Bit range	R/W	Description
DATA	7-0	RW	Read: Byte shifted in. Write: Byte to shift out.

5.1.3. CNTR (0x9049c008)

Control register.

When IFLG is set, the internal state machine is paused. Resetting the IFLG bit acknowledged the interrupt and advances the state machine to its next state.

Symbol	Bit range	R/W	Description
IEN	7	RW	Enable interrupts. 0: Interrupt line is kept low. 1: Interrupt line becomes high as long as IFLG is set.
ENAB	6	RW	Bus enable. 0: SDA and SCL state is ignored. 1: Respond to own address (and general call, if enabled) in slave mode. Must be set in multi-master mode to support arbitration.
STA	5	RW	Writing a 1 causes the controller to enter master mode and send a START condition. If the controller was already in master mode, a repeated start condition is sent. If a transaction was occuring in slave mode at the time 1 was written to STA, the transaction is completed first. The STA bit is cleared automatically after sending the START condition.
STP	4	RW	Writing a 1 causes the controller in master mode to send a STOP condition and leave master mode. Writing a 1 in slave mode will stop the transaction, as if the remote master had sent a STOP condition. When writing 1 to both STA and STP, the controller applies STP then STA (the effect is that the current transaction, either master or slave, is aborted, and a START condition is sent). STP is reset automatically on completion.
IFLG	3	RW	Interrupt flag. This flag is automatically set when the value of the STAT register changes, except when it transition to the idle state (0xf8). If IEN is 1, the interrupt line is held high as long as IFLG is set. Acknowledging the interrupt is done by writing a value to CNTR with the IFLG flag set to 0. This will make the internal state machine transition to the next state. When in slave mode, the current transfer is paused (SCL is held low, which is known as clock stretching) until the interrupt is acknowledged. Writing 1 to IFLG has no effect.
AAK	2	RW	Assert acknowlegde. Writing a 1 in AAK will cause a controller to acknowledge (drive SDA low) a received byte. In slave mode, setting AAK to 1 will cause the controller to acknowledge the address part of the transaction if the address matches its own (or the general call address, if enabled). Writing 0 will cause the controller to leave SDA floating (send a NACK).
reserved	1-0	RW	Reserved

5.1.4. STAT (0x9049c00c)

Status register.

Symbol	Bit range	R/W	Description
STAT	7-0	R	Status information byte. See list below.

Meaning of the STAT information byte:

Code	Mnemonic	Meaning
0x00	BUS_ERROR	Bus error
0x08	START	Start condition transmitted
0x10	START_REPEATED	Repeated start condition transmitted
0x18	ADDR_WR_ACK	Address + Write bit transmitted, ACK received
0x20	ADDR_WR_NACK	Address + Write bit transmitted, NACK received
0x28	DATA_WR_ACK	Data byte transmitted in master mode, ACK received
0x30	DATA_WR_NACK	Data byte transmitted in master mode, NACK received
0x38	ARBIT_LOST	Arbitration lost in address or data byte
0x40	ADDR_RD_ACK	Address + Read bit transmitted, ACK received
0x48	ADDR_RD_NACK	Address + Read bit transmitted, NACK received
0x50	DATA_RD_ACK	Data byte received in master mode, ACK transmitted
0x58	DATA_RD_NACK	Data byte received in master mode, NACK transmitted
0x60	SLVADDR_WR	Slave address + Write bit received, ACK transmitted
0x68	ARBIT_LOST_SLVADDR_WR	Arbitration lost in address as master, slave address + Write bit received, ACK transmitted
0x70	GENCALL	General Call address received, ACK transmitted
0x78	ARBIT_LOST_GENCALL	Arbitration lost in address as master, General Call address received, ACK transmitted
0x80	SLVADDR_DATA_RX_ACK	Data byte received after slave address received, ACK transmitted
0x88	SLVADDR_DATA_RX_NACK	Data byte received after slave address received, not ACK transmitted
0x90	GENCALL_DATA_RX_ACK	Data byte received after General Call received, ACK transmitted
0x98	GENCALL_DATA_RX_NACK	Data byte received after General Call received, not ACK transmitted
0xa0	SVL_STOP	STOP or repeated START condition received in slave mode
0xa8	SLVADDR_RD	Slave address + Read bit received, ACK transmitted
0xb0	ARBIT_LOST_SLVADDR_RD	Arbitration lost in address as master, slave address + Read bit received, ACK transmitted
0xb8	SLV_DATA_TX_ACK	Data byte transmitted in slave mode, ACK received
0xc0	SLV_DATA_TX_NACK	Data byte transmitted in slave mode, ACK not received
0xc8	SLV_DATA_LAST_TX_ACK	Last byte transmitted in slave mode, ACK received
0xd0	XADDR_WR_ACK	Second Address byte + Write bit transmitted, ACK received
0xd8	XADDR_WR_NACK	Second Address byte + Write bit transmitted, ACK not received
0xf8	NO_RELEVANT_INFO	No relevant status information, IFLF=0

5.1.5. CCRFS (0x9049c00c)

Clock control register for full speed operation.

If you need to perform master mode transactions in full-speed mode, write the divider values into this register instead of CCRH.

Symbol	Bit range	R/W	Description
M	6-3	RW	Clock divider (0-15)
N	2-0	RW	Clock prescaler (0-7)

Fout = Fin / (2^N * (M + 1) * 10)

Fin is the frequency of the AXI clock.

E.g: For an AXI clock Fin of 250 MHz, a prescaler value N of 7 and a divider value M of 1:

Fout = Fin / (2^N * (M + 1) * 10)
Fout = 250000000 / (2^7 * (1 + 1) * 10)
Fout = 250000000 / (128 * 2 * 10)
Fout = 250000000 / 2560
Fout = 97656,25 Hz

5.1.6. XADDR (0x9049c010)

Low 8 bits of the 10-bit own address.

For this register to be of any use, the 10-bit addressing prefix and the higher 2 bits of the 10-bit address must be written into the SLA field of the ADDR register. Only then will 10 bit addressing mode be enabled.

Symbol	Bit range	R/W	Description
SLAX	7-0	RW	Lower 8 bits of the extended 10-bit own address.

5.1.7. CCRH (0x9049c004)

Clock control register for high speed operation.

If you need to perform master mode transactions in high-speed mode, write the divider values into this register instead of CCRFS.

Symbol	Bit range	R/W	Description
M	6-3	RW	Clock divider (0-15)
N	2-0	RW	Clock prescaler (0-7)

Fout = Fin / (2^N * (M + 1) * 10)

Fin is the frequency of the AXI clock.

5.1.8. RESET (0x9049c01c)

Software reset register.

Symbol	Bit range	R/W	Description
SOFT_RST	0	RW	Write 1 to perform a software reset. Automatically cleared when reset is complete.

6. Clock and reset controller

4 PLLs
- PLLs 0, 1 & 2 up to 2 GHz
- PLL 3 up to 1.2 GHz with dithering support for DDR
- All PLLs can be bypassed to use the reference clock instead of the PLL output
- PLLs 0 & 1 have a divider on their output for frequency scaling
- Per-peripheral (clock domain) configurable clock input and divider
2 NCOs
GEM PHY, DECT BCLK & PCIe reference clocks outputs
AHB/APB clock is AXI/4

6.1. Reference clock

The C2000 chip accepts a 24 or 48 MHz crystal or clock as external reference clock for the system PLLs and SerDes. Bootstrap pins allow to select between crystal/clock and 24/48 MHz.

The datasheet also mentions that it is theoretically possible to use a 125 MHz reference clock from the SerDes block, but since the SerDes clocks are not provided during reset, such a configuration would never boot.

An internal reference clock is derived from the external reference clock. It is the same, except for the unusable 125 MHz case, where it is divided by 6. That internal reference clock can be used as clock source for peripherals.

6.2. PLLs

The C2000 chip features 4 programmable PLLs.

The input clock is the raw external reference clock.

All PLLs have those 3 parameters:

M: 10-bit (9-bit for PLL 3) main divider (or multiplier depending on how you see it) value
P: 6-bit pre-divider value
S: 3-bit post-scaler value

PLL 3 uses an additional 12-bit parameter, K, which is used to precisely to add a fractional divider to the main divider.

A global PLL bypass mechanism, separate from each PLL's own bypass mechanism allows to feed the reference clock directly to the clock generator of all peripherals, in lieu of the PLL output.

This PLL global bypass not only bypasses the PLLs themselves, but also, for PLLs 0 & 1, the divider immediately after them.

6.2.1. PLLs 0, 1 & 2

Maximum rate: 2.0 GHz

Output frequency formula: Fout = (Fref * M) / (P * 2^S)

PLL 0 & 1 outputs can be divided further. The divider value can be configured using the PLLx_DIV_CNTRL registers.

6.2.2. PLL 3

Maximum rate: 1.2 GHz

Output frequency formula from manufacturer's Linux code (in MHz):

Fout = ((Fref / 1000000) * ((M * 1024) + K) / P / 2^S + 1023) / 1024

The value is rounded up to the upper MHz to "look nice", losing some precision in the process.

My guess on what the actual formula may look like:

Fout = Fref * (M + K / 1024) / (P * 2^S)

Bootloader settings for PLL3_CFG_1066 for 48 MHz refclk.
M=87
P=4
S=0
d=4
K=1877

Result with original formula: 1065996094,749023438 Hz

PLL 3 supports dithering (spread spectrum).

6.3. Registers

Base address	0x904b0000
Size	0x00000400

Symbol	Offset	Description
DEVICE_RST_CNTRL	0x0000
SERDES_RST_CNTRL	0x0004
PCIe_SATA_RST_CNTRL	0x0008
USB_RST_CNTRL	0x000c
GNRL_DEVICE_CNFG_0	0x0010
GNRL_DEVICE_CNFG_1	0x0014
GNRL_DEVICE_STATUS	0x0018
A9DP_PWR_STAT	0x0028
A9DP_PWR_CNTRL	0x002c
GNRL_CLK_CNTRL_0	0x0030
GNRL_CLK_CNTRL_1	0x0034
PLLS_GLOBAL_CNTRL	0x0038
AXI_CLK_CNTRL_0	0x0040
AXI_CLK_CNTRL_1	0x0044
AXI_CLK_CNTRL_2	0x0048
AXI_CLK_DIV_CNTRL	0x004c
AXI_RESET_0	0x0050
AXI_RESET_1	0x0054
AXI_RESET_2	0x0058
A9DP_MPU_CLK_CNTRL	0x0068
A9DP_MPU_CLK_DIV_CNTRL	0x006c
A9DP_MPU_RESET	0x0070
A9DP_CPU_CLK_CNTRL	0x0074
A9DP_CPU_RESET	0x0078
A9DP_CLK_CNTRL	0x0080
A9DP_CLK_DIV_CNTRL	0x0084
A9DP_RESET	0x0088
L2CC_CLK_CNTRL	0x0090
L2CC_CLK_DIV_CNTRL	0x0094
L2CC_RESET	0x0098
TPI_CLK_CNTRL	0x00a0
TPI_CLK_DIV_CNTRL	0x00a4
TPI_RESET	0x00a8
CSYS_CLK_CNTRL	0x00b0
CSYS_CLK_DIV_CNTRL	0x00b4
CSYS_RESET	0x00b8
EXTPHY0_CLK_CNTRL	0x00c0
EXTPHY0_CLK_DIV_CNTRL	0x00c4
EXTPHY0_RESET	0x00c8
EXTPHY1_CLK_CNTRL	0x00d0
EXTPHY1_CLK_DIV_CNTRL	0x00d4
EXTPHY1_RESET	0x00d8
EXTPHY2_CLK_CNTRL	0x00e0
EXTPHY2_CLK_DIV_CNTRL	0x00e4
EXTPHY2_RESET	0x00e8
DDR_CLK_CNTRL	0x00f0
DDR_CLK_DIV_CNTRL	0x00f4
DDR_RESET	0x00f8
PFE_CLK_CNTRL	0x0100
PFE_CLK_DIV_CNTRL	0x0104
PFE_RESET	0x0108	PFE core reset
IPSEC_CLK_CNTRL	0x0110
IPSEC_CLK_DIV_CNTRL	0x0114
IPSEC_RESET	0x0118
DECT_CLK_CNTRL	0x0120
DECT_CLK_DIV_CNTRL	0x0124
DECT_RESET	0x0128
GEMTX_CLK_CNTRL	0x0130
GEMTX_CLK_DIV_CNTRL	0x0134
GEMTX_RESET	0x0138
TDMNTG_REF_CLK_CNTRL	0x0140
TDMNTG_REF_CLK_DIV_CNTRL	0x0144
TDMNTG_RESET	0x0148
TDM_CLK_CNTRL	0x014c
TSUNTG_REF_CLK_CNTRL	0x0150
TSUNTG_REF_CLK_DIV_CNTRL	0x0154
TSUNTG_RESET	0x0158
SATA_PMU_CLK_CNTRL	0x0160
SATA_PMU_CLK_DIV_CNTRL	0x0164
SATA_PMU_RESET	0x0168
SATA_OOB_CLK_CNTRL	0x0170
SATA_OOB_CLK_DIV_CNTRL	0x0174
SATA_OOB_RESET	0x0178
SATA_OCC_CLK_CNTRL	0x0180
SATA_OCC_CLK_DIV_CNTRL	0x0184
SATA_OCC_RESET	0x0188
PCIE_OCC_CLK_CNTRL	0x0190
PCIE_OCC_CLK_DIV_CNTRL	0x0194
PCIE_OCC_RESET	0x0198
SGMII_OCC_CLK_CNTRL	0x01a0
SGMII_OCC_CLK_DIV_CNTRL	0x01a4
SGMII_OCC_RESET	0x01a8
PLL0_M_LSB	0x01c0
PLL0_M_MSB	0x01c4
PLL0_P	0x01c8
PLL0_S	0x01cc
PLL0_CNTRL	0x01d0
PLL0_TEST	0x01d4
PLL0_STATUS	0x01d8
PLL0_DIV_CNTRL	0x01dc
PLL1_M_LSB	0x01e0
PLL1_M_MSB	0x01e4
PLL1_P	0x01e8
PLL1_S	0x01ec
PLL1_CNTRL	0x01f0
PLL1_TEST	0x01f4
PLL1_STATUS	0x01f8
PLL1_DIV_CNTRL	0x01fc
PLL2_M_LSB	0x0200
PLL2_M_MSB	0x0204
PLL2_P	0x0208
PLL2_S	0x020c
PLL2_CNTRL	0x0210
PLL2_TEST	0x0214
PLL2_STATUS	0x0218
PLL3_M_LSB	0x0220
PLL3_M_MSB	0x0224
PLL3_P	0x0228
PLL3_S	0x022c
PLL3_CNTRL	0x0230
PLL3_TEST	0x0234
PLL3_STATUS	0x0238
PLL3_DITHER_CNTRL	0x023c
PLL3_K_LSB	0x0240
PLL3_K_MSB	0x0244
PLL3_MFR	0x0248
PLL3_MRR	0x024c
TDMNTG_ADDR_SPACE_BASEADDR	0x0280
TSUNGTG_ADDR_SPACE_BASEADDR	0x02c0

6.3.1. DEVICE_RST_CNTRL (0x904b0000)

Global device reset register.

Symbol	Bit range	R/W	Description
CLK_DIV_RESTART	7	RW	Clock divider restart. Self-clearing
WD_STATUS_CLR	6	W	Clear AXI watchdog status (see GNRL_DEVICE_STATUS)
AXI_WD_RST_EN	5	RW	Enable reset on AXI watchdog timer block
DEBUG_RST	4	RW	Reset (disable) debug features (CoreSight and ARM debug). Does not self-clear
CLKRST_SCLR_RST	3	RW	Reset clocks? Self-clearing?
FUNC_SCLR_RST	2	RW	Perform a functional software reset. Reset all blocks except PLLs, clocks, reset and debug logic. Maybe self-clearing (if CLKRST_SCLR_RST is set at the sme time?)
GLB_SCLR_RST	1	RW	Global reset. Self-clearing. Same as PWR_ON_SOFT_RST, but does not reset debug.
PWR_ON_SOFT_RST	0	RW	Power on software reset. Self-clearing

6.3.2. SERDES_RST_CNTRL (0x904b0004)

SerDes reset register.

Symbol	Bit range	R/W	Description
	7-3	RW	Reserved. Write as 1.
SERDES2_RESET	2	RW	SerDes 2 reset state
SERDES1_RESET	1	RW	SerDes 1 reset state
SERDES0_RESET	0	RW	SerDes 0 reset state

6.3.3. PCIe_SATA_RST_CNTRL (0x904b0008)

PCIe & SATA reset register.

Symbol	Bit range	R/W	Description
SATA1_TX_RST	7	RW	SATA1 SerDes Tx reset
SATA1_RX_RST	6	RW	SATA1 SerDes Rx reset
SATA0_TX_RST	5	RW	SATA0 SerDes Tx reset
SATA0_RX_RST	4	RW	SATA0 SerDes Rx reset
PCIE1_REG_RST	3	RW	PCIe1 controller reset?
PCIE1_PWR_RST	2	RW	PCIe1 power domain reset?
PCIE0_REG_RST	1	RW	PCIe0 controller reset?
PCIE0_PWR_RST	0	RW	PCIe0 power domain reset?

Note: Asserting and deasserting PCIEx_PWR_RST also resets the PCIe registers.

6.3.4. USB_RST_CNTRL (0x904b000c)

USB reset register.

UTMI is the interface between the USB controller and the USB PHY.

Symbol	Bit range	R/W	Description
USB1_UTMI_RESET	5	RW	USB1 UTMI reset
USB1_PHY_RESET	4	RW	USB1 PHY reset
USB0_UTMI_RESET	1	RW	USB0 UTMI reset
USB0_PHY_RESET	0	RW	USB0 PHY reset

6.3.5. GNRL_DEVICE_CNFG_0 (0x904b0010)

General device configuration register 0.

Symbol	Bit range	R/W	Description

6.3.6. GNRL_DEVICE_CNFG_1 (0x904b0014)

General device configuration register 1.

Symbol	Bit range	R/W	Description

6.3.7. GNRL_DEVICE_STATUS (0x904b0018)

General device status register.

Symbol	Bit range	R/W	Description
CPU1_WD_RST_ACTIVATED	2	R	Reset caused by CPU1 watchdog?
CPU0_WD_RST_ACTIVATED	1	R	Reset caused by CPU0 watchdog?
AXI_WD_RST_ACTIVATED	0	R	Reset caused by AXI watchdog. Can be cleared by setting the WD_STATUS_CLR bit in DEVICE_RST_CNTRL.

6.3.8. A9DP_PWR_STAT (0x904b0028)

6.3.9. A9DP_PWR_CNTRL (0x904b002c)

A9DP block power control register.

Symbol	Bit range	R/W	Description
CORE_PWRDWN1	7	R/W	Power down CPU1 power domain
CLAMP_CORE1	6	R/W	Isolate CPU1?
CORE_PWRDWN0	5	R/W	Power down CPU0 power domain
CLAMP_CORE0	4	R/W	Isolate CPU0?
MP_POWERDOWN	0	R/W	Power down the full MP block (all cores + SCU + A9 periph.)

6.3.10. GNRL_CLK_CNTRL_0 (0x904b0030)

6.3.11. GNRL_CLK_CNTRL_1 (0x904b0034)

General clock control register 1

Set to 0xd1, then 0xd0 in bootloader.

Symbol	Bit range	R/W	Description
GLOBAL_BYPASS	0	RW	(DANGEROUS!) Global bypass. All the clock dividers are bypassed. Overrides the individual clock generators bypass setting. It is unclear which clock generators are effected. Used by bootloader. NEVER SET WHILE THE PLLS ARE RUNNING!

6.3.12. PLLS_GLOBAL_CNTRL (0x904b0038)

Global PLL bypass register.

Symbol	Bit range	R/W	Description
PLL3	3	RW	PLL3 bypass. 0: Use PLL output 1: Use int_ref_clk output
PLL2	2	RW	PLL2 bypass. 0: Use PLL output 1: Use int_ref_clk output
PLL1	1	RW	PLL1 bypass. 0: Use PLL output 1: Use int_ref_clk output
PLL0	0	RW	PLL0 bypass. 0: Use PLL output 1: Use int_ref_clk output

6.3.13. AXI_CLK_CNTRL_0 (0x904b0040)

AXI interface clock control register 0.

Symbol	Bit range	R/W	Description
?	7	R/W	Something important. Keep enabled.
DPI_DECOMP_CLK_ENABLE	6	R/W	Enable clock domain for DPI decompression engine
DPI_CIE_CLK_ENABLE	5	R/W	Enable clock domain for DPI Content Inspection Engine
?_CLK_ENABLE	4	R/W	Enable clock domain for something important. DDR? DMA?
CLOCK_SOURCE	3-1	R/W	Clock source selection. 0: PLL0 1: PLL1 2: PLL2 3: PLL3 4: internal refclk (24/48 MHz)
CLOCK_DOMAIN_ENABLE	0	R/W	Enable AXI clock domain.

6.3.14. AXI_CLK_CNTRL_1 (0x904b0044)

AXI interface clock control register 1.

Symbol	Bit range	R/W	Description
RTC_TIM_CLK_ENABLE	7	R/W	Enable clock domain for the RTC and timer blocks
UART_CLK_ENABLE	6	R/W	Enable legacy UART clock domain.
I2CSPI_CLK_ENABLE	5	R/W	Enable clock domain for slow I2C/SPI controllers.
TDM_CLK_ENABLE	4	R/W	Enable clock domain for the TDM device.
PFE_SYS_CLK_ENABLE	3	R/W	Enable SYS clock domain for the Packet Forwarding Engine.
IPSEC_SPACC_CLK_ENABLE	2	R/W	Enable clock domain for the IPSec Security Protocol Accelerator.
IPSEC_EAPE_CLK_ENABLE	1	R/W	Enable clock domain for the IPSec EAP engine.
DUS_CLK_ENABLE	0	R/W	Enable clock domain for the DUSI subsystem (fast UART, fast I2C, fast SPI and I2S).

6.3.15. AXI_CLK_CNTRL_2 (0x904b0048)

AXI interface clock control register 2.

Symbol	Bit range	R/W	Description
?	7	R/W	Unknown. Not critical
?	6	R/W	Unknown. Not critical
?	5	R/W	Unknown. Probably something important since the system hangs if cleared. DDR? DMA?
USB1_CLK_ENABLE	4	R/W	Enable clock domain for the USB1 (USB 3.0) device.
USB0_CLK_ENABLE	3	R/W	Enable clock domain for the USB0 (USB 2.0) device.
SATA_CLK_ENABLE	2	R/W	Enable clock domain for the SATA device.
PCIE1_CLK_ENABLE	1	R/W	Enable clock domain for the PCIE1 device.
PCIE0_CLK_ENABLE	0	R/W	Enable clock domain for the PCIE0 device.

6.3.16. AXI_CLK_DIV_CNTRL (0x904b004c)

6.3.17. AXI_RESET_0 (0x904b0050)

AXI interface reset register 0.

Symbol	Bit range	R/W	Description
DPI_DECOMP_RST	6	R/W	Reset AXI clock domain for DPI decompression engine
DPI_CIE_RST	5	R/W	Reset AXI clock domain for DPI Content Inspection Engine
?_RST	4	R/W	Reset for something important

6.3.18. AXI_RESET_1 (0x904b0054)

AXI interface reset register 1.

Symbol	Bit range	R/W	Description
RTC_TIM_RST	7	R/W	Reset AXI clock domain for the RTC and timer blocks.
UART_RST	6	R/W	Legacy UART reset.
I2CSPI_RST	5	R/W	Reset AXI clock domain for slow I2C/SPI controllers.
TDM_RST	4	R/W	Reset AXI clock domain for the TDM device.
PFE_SYS_RST	3	R/W	Reset AXI clock domain for the Packet Forwarding Engine.
IPSEC_SPACC_RST	2	R/W	Reset AXI clock domain for the IPSec Security Protocol Accelerator.
IPSEC_EAPE_RST	1	R/W	Reset AXI clock domain for the IPSec EAP engine.
DUS_RST	0	R/W	Reset AXI clock domain for the DUSI subsystem (fast UART, fast I2C, fast SPI and I2S).

6.3.19. AXI_RESET_2 (0x904b0058)

AXI interface reset register 2.

Symbol	Bit range	R/W	Description
?	5	R/W	Unknown. Probably something important since the system hangs if set.
USB1_RST	4	R/W	Reset AXI clock domain for the USB1 (USB 3.0) device.
USB0_RST	3	R/W	Reset AXI clock domain for the USB0 (USB 2.0) device.
SATA_RST	2	R/W	Reset AXI clock domain for the SATA device.
PCIE1_RST	1	R/W	Reset AXI clock domain for the PCIE1 device.
PCIE0_RST	0	R/W	Reset AXI clock domain for the PCIE0 device.

6.3.20. A9DP_MPU_CLK_CNTRL (0x904b0068)

A9 peripherals clock control.

Symbol	Bit range	R/W	Description
?	7	R/W	Unknown. Set by default.
GIC_CLK_ENABLE	6	R/W	Enable/disable interrupt controller clock.

6.3.21. A9DP_MPU_CLK_DIV_CNTRL (0x904b006c)

A9 peripherals clock divider control register?

Default value is 0. Never changed. ARM peripherals clock is always divided by at least 4.

6.3.22. A9DP_MPU_RESET (0x904b0070)

Reset register for the A9 MPU block. Probably to reset blocks other than the CPU cores themselves (i.e. SCU and A9 peripherals).

Symbol	Bit range	R/W	Description
?	7	R/W	No visible effect.
GIC_RST	6	R/W	Reset interrupt controller (GIC)
?	5	R/W	No visible effect.
?	4	R/W	Reset ?.
?	3	R/W	No visible effect.
?	2	R/W	Reset ?.
?	1	R/W	No visible effect.
?	0	R/W	Reset ?.

6.3.23. A9DP_CPU_CLK_CNTRL (0x904b0074)

CPU clock control register.

Symbol	Bit range	R/W	Description
NEON1_CLK_ENABLE	3	R/W	Enable/disable CPU1 NEON coprocessor clock
CPU1_CLK_ENABLE	2	R/W	Enable/disable CPU1 clock
NEON0_CLK_ENABLE	1	R/W	Enable/disable CPU0 NEON coprocessor clock
CPU0_CLK_ENABLE	0	R/W	Enable/disable CPU0 clock

6.3.24. A9DP_CPU_RESET (0x904b0078)

CPU cores block reset register.

Symbol	Bit range	R/W	Description
NEON1_RST	3	R/W	CPU1 NEON coprocessor reset.
CPU1_RST	2	R/W	CPU1 core reset.
NEON0_RST	1	R/W	CPU0 NEON coprocessor reset.
CPU0_RST	0	R/W	CPU0 core reset.

6.3.25. A9DP_CLK_CNTRL (0x904b0080)

A9 subsystem clock control register.

See description for XXX_CLK_CNTRL.

6.3.26. A9DP_CLK_DIV_CNTRL (0x904b0084)

A9 subsystem clock divider control register.

See description for XXX_CLK_DIV_CNTRL.

6.3.27. A9DP_RESET (0x904b0088)

Reset register for the full A9 subsystem (CPU cores + SCU + A9 peripherals + L2CC? + Coresight)?

Symbol	Bit range	R/W	Description
A9DP_RST	0	R/W	Reset full A9 subsystem?

6.3.28. L2CC_CLK_CNTRL (0x904b0090)

L2CC clock control register.

Symbol	Bit range	R/W	Description
L2CC_CLOCK_SOURCE	3-1	R/W	0-7: A9 subsystem clock (presumably, and according to the clock diagram. Tests shows that it is NOT PLL0-3, nor ref clock)
L2CC_CLK_ENABLE	0	R/W	Enable L2CC clock.

6.3.29. L2CC_CLK_DIV_CNTRL (0x904b0094)

L2CC clock divider control register.

See XXX_CLK_DIV_CNTRL description.

6.3.30. L2CC_RESET (0x904b0098)

L2CC reset register.

Symbol	Bit range	R/W	Description
L2CC_RST	0	R/W	Put the L2CC device in reset state. 0=leave reset, 1=enter reset

6.3.31. TPI_CLK_CNTRL (0x904b00a0)

6.3.32. TPI_CLK_DIV_CNTRL (0x904b00a4)

6.3.33. TPI_RESET (0x904b00a8)

TPI (Trace Port Interface) reset register.

Symbol	Bit range	R/W	Description
TPI_RST	0	R/W	Put the TPI device in reset state. 0=leave reset, 1=enter reset

6.3.34. CSYS_CLK_CNTRL (0x904b00b0)

6.3.35. CSYS_CLK_DIV_CNTRL (0x904b00b4)

6.3.36. CSYS_RESET (0x904b00b8)

CSYS (CoreSight) reset register.

Symbol	Bit range	R/W	Description
CSYS_RST	0	R/W	Put the CSYS device in reset state. 0=leave reset, 1=enter reset

6.3.37. EXTPHY0_CLK_CNTRL (0x904b00c0)

6.3.38. EXTPHY0_CLK_DIV_CNTRL (0x904b00c4)

6.3.39. EXTPHY0_RESET (0x904b00c8)

EXT0 PHY reset register.

Symbol	Bit range	R/W	Description
EXT0PHY_RST	0	R/W	Put the EXT0 PHY in reset state. 0=leave reset, 1=enter reset

6.3.40. EXTPHY1_CLK_CNTRL (0x904b00d0)

6.3.41. EXTPHY1_CLK_DIV_CNTRL (0x904b00d4)

6.3.42. EXTPHY1_RESET (0x904b00d8)

EXT1 PHY reset register.

Symbol	Bit range	R/W	Description
EXT1PHY_RST	0	R/W	Put the EXT1 PHY in reset state. 0=leave reset, 1=enter reset

6.3.43. EXTPHY2_CLK_CNTRL (0x904b00e0)

6.3.44. EXTPHY2_CLK_DIV_CNTRL (0x904b00e4)

6.3.45. EXTPHY2_RESET (0x904b00e8)

EXT2 PHY reset register.

Symbol	Bit range	R/W	Description
EXT2PHY_RST	0	R/W	Put the EXT2 PHY in reset state. 0=leave reset, 1=enter reset

6.3.46. DDR_CLK_CNTRL (0x904b00f0)

6.3.47. DDR_CLK_DIV_CNTRL (0x904b00f4)

6.3.48. DDR_RESET (0x904b00f8)

DDR reset register.

Symbol	Bit range	R/W	Description
DDRCNTRL_RST	1	R/W	Put the DDR controller in reset state. 0=leave reset, 1=enter reset
DDRPHY_RST	0	R/W	Put the DDR PHY in reset state. 0=leave reset, 1=enter reset

6.3.49. PFE_CLK_CNTRL (0x904b0100)

6.3.50. PFE_CLK_DIV_CNTRL (0x904b0104)

6.3.51. PFE_RESET (0x904b0108)

PFE core reset register.

Symbol	Bit range	R/W	Description
PFE_CORE_RST	0	R/W	Put the PFE core in reset state. 0=leave reset, 1=enter reset

6.3.52. IPSEC_CLK_CNTRL (0x904b0110)

6.3.53. IPSEC_CLK_DIV_CNTRL (0x904b0114)

6.3.54. IPSEC_RESET (0x904b0118)

IPSEC core reset register.

Symbol	Bit range	R/W	Description
IPSEC_EAPE_CORE_RST	0	R/W	Put the IPSEC EAPE core into reset state. 0=leave reset, 1=enter reset

6.3.55. DECT_CLK_CNTRL (0x904b0120)

6.3.56. DECT_CLK_DIV_CNTRL (0x904b0124)

6.3.57. DECT_RESET (0x904b0128)

DECT device reset register.

Symbol	Bit range	R/W	Description
DECT_RST	0	R/W	Put the DECT device into reset state. 0=leave reset, 1=enter reset

6.3.58. GEMTX_CLK_CNTRL (0x904b0130)

6.3.59. GEMTX_CLK_DIV_CNTRL (0x904b0134)

6.3.60. GEMTX_RESET (0x904b0138)

GEMTX device reset register.

Symbol	Bit range	R/W	Description
GEMTX_RST	0	R/W	Put the GEMTX device into reset state. 0=leave reset, 1=enter reset

6.3.61. TDMNTG_REF_CLK_CNTRL (0x904b0140)

6.3.62. TDMNTG_REF_CLK_DIV_CNTRL (0x904b0144)

6.3.63. TDMNTG_RESET (0x904b0148)

TDMNTG (Time Division Multiplexing Network Timer Generator) device reset register.

Symbol	Bit range	R/W	Description
TDMNTG_RST	0	R/W	Put the TDMNTG device into reset state. 0=leave reset, 1=enter reset

6.3.64. TDM_CLK_CNTRL (0x904b014c)

6.3.65. TSUNTG_REF_CLK_CNTRL (0x904b0150)

6.3.66. TSUNTG_REF_CLK_DIV_CNTRL (0x904b0154)

6.3.67. TSUNTG_RESET (0x904b0158)

TSU NTG (TimeStamp Unit Network Timing Generator) device reset register.

Symbol	Bit range	R/W	Description
TSUNTG_RST	0	R/W	Put the TSUNTG device into reset state. 0=leave reset, 1=enter reset

6.3.68. SATA_PMU_CLK_CNTRL (0x904b0160)

6.3.69. SATA_PMU_CLK_DIV_CNTRL (0x904b0164)

6.3.70. SATA_PMU_RESET (0x904b0168)

SATA_PMU device (keep alive clock) reset register.

Symbol	Bit range	R/W	Description
SATA_PMU_RST	0	R/W	Put the SATA_PMU device into reset state. 0=leave reset, 1=enter reset

6.3.71. SATA_OOB_CLK_CNTRL (0x904b0170)

6.3.72. SATA_OOB_CLK_DIV_CNTRL (0x904b0174)

6.3.73. SATA_OOB_RESET (0x904b0178)

SATA_OOB device (keep alive clock) reset register.

Symbol	Bit range	R/W	Description
SATA_OOB_RST	0	R/W	Put the SATA_OOB device into reset state. 0=leave reset, 1=enter reset

6.3.74. SATA_OCC_CLK_CNTRL (0x904b0180)

6.3.75. SATA_OCC_CLK_DIV_CNTRL (0x904b0184)

6.3.76. SATA_OCC_RESET (0x904b0188)

SATA OCC reset register.

Symbol	Bit range	R/W	Description
SATA_OCC_RST	0	R/W	Put the SATA_OCC device into reset state. 0=leave reset, 1=enter reset

6.3.77. PCIE_OCC_CLK_CNTRL (0x904b0190)

6.3.78. PCIE_OCC_CLK_DIV_CNTRL (0x904b0194)

6.3.79. PCIE_OCC_RESET (0x904b0198)

PCIE OCC reset register.

Symbol	Bit range	R/W	Description
PCIE_OCC_RST	0	R/W	Put the PCIE_OCC device into reset state. 0=leave reset, 1=enter reset

6.3.80. SGMII_OCC_CLK_CNTRL (0x904b01a0)

6.3.81. SGMII_OCC_CLK_DIV_CNTRL (0x904b01a4)

6.3.82. SGMII_OCC_RESET (0x904b01a8)

SGMII OCC reset register.

Symbol	Bit range	R/W	Description
SGMII_OCC_RST	0	R/W	Put the SGMII_OCC device into reset state. 0=leave reset, 1=enter reset

6.3.83. PLL0_M_LSB (0x904b01c0)

6.3.84. PLL0_M_MSB (0x904b01c4)

6.3.85. PLL0_P (0x904b01c8)

6.3.86. PLL0_S (0x904b01cc)

6.3.87. PLL0_CNTRL (0x904b01d0)

6.3.88. PLL0_TEST (0x904b01d4)

6.3.89. PLL0_STATUS (0x904b01d8)

6.3.90. PLL0_DIV_CNTRL (0x904b01dc)

6.3.91. PLL1_M_LSB (0x904b01e0)

6.3.92. PLL1_M_MSB (0x904b01e4)

6.3.93. PLL1_P (0x904b01e8)

6.3.94. PLL1_S (0x904b01ec)

6.3.95. PLL1_CNTRL (0x904b01f0)

6.3.96. PLL1_TEST (0x904b01f4)

6.3.97. PLL1_STATUS (0x904b01f8)

6.3.98. PLL1_DIV_CNTRL (0x904b01fc)

6.3.99. PLL2_M_LSB (0x904b0200)

6.3.100. PLL2_M_MSB (0x904b0204)

6.3.101. PLL2_P (0x904b0208)

6.3.102. PLL2_S (0x904b020c)

6.3.103. PLL2_CNTRL (0x904b0210)

6.3.104. PLL2_TEST (0x904b0214)

6.3.105. PLL2_STATUS (0x904b0218)

6.3.106. PLL2_DIV_CNTRL (0x904b021c)

6.3.107. PLL3_M_LSB (0x904b0220)

PLL main divider (M) value (lower 8 bits).

Symbol	Bit range	R/W	Description
M_LSB	7-0	RW	M low bits

6.3.108. PLL3_M_MSB (0x904b0224)

PLL main divider (M) value (higher 1 bit).

Symbol	Bit range	R/W	Description
M_MSB	0	RW	M high bit

6.3.109. PLL3_P (0x904b0228)

6.3.110. PLL3_S (0x904b022c)

6.3.111. PLL3_CNTRL (0x904b0230)

6.3.112. PLL3_TEST (0x904b02234)

6.3.113. PLL3_STATUS (0x904b0238)

6.3.114. PLL3_DITHER_CNTRL (0x904b023c)

Dithering control register? Set to 0x00 in bootloader.

6.3.115. PLL3_K_LSB (0x904b0240)

Symbol	Bit range	R/W	Description
K	7-0	RW	K parameter lower byte

6.3.116. PLL3_K_MSB (0x904b0244)

Symbol	Bit range	R/W	Description
K	3-0	RW	K parameter higher byte

6.3.117. PLL3_MFR (0x904b0248)

Unknown. Set to 0x01 in bootloader.

6.3.118. PLL3_MRR (0x904b024c)

Unknown and unused. Set to 0x07 in bootloader.

6.3.119. TDMNTG_ADDR_SPACE_BASEADDR (0x904b0280)

6.3.120. TSUNTG_ADDR_SPACE_BASEADDR (0x904b02c0)

6.3.121. XXX_CLK_CNTRL

Peripheral clock control register.

Symbol	Bit range	R/W	Description
CLOCK_SOURCE	1-3	R/W	Clock source selection: 0: PLL0, 1: PLL1, 2: PLL2, 3: PLL3, 4: internal refclk (24/48 MHz)
CLOCK_DOMAIN_ENABLE	0	R/W	Enable/disable clock domain. 0: disable, 1: enable

6.3.122. XXX_CLK_DIV_CNTRL

Peripheral clock divider control register.

WARNING: A hardware bug prevents reading the divider BYPASS bit. This bit will read as zero. A software workaround is to keep track of what value the software writes into the BYPASS bit of the XXX_CLK_DIV_CNTRL registers into a RAM region. Barebox keeps this info in IRAM, while Linux uses the DDR.

Symbol	Bit range	R/W	Description
BYPASS	7	W	Enable/disable divider bypass. 0=apply divider, 1=bypass
DIVIDER	0-4	RW	Clock divider value. Values 0 and 1 are reserved will not work as expected. Please set the BYPASS bit instead of setting DIVIDER to 1.

6.3.123. XXX_RESET

Peripheral reset register.

6.3.124. PLLx_M_LSB

PLL main divider (M) value (lower 8 bits).

Applies to PLLs 0-2.

Symbol	Bit range	R/W	Description
M_LSB	7-0	RW	M low bits

6.3.125. PLLx_M_MSB

PLL main divider (M) value (higher 2 bits).

Applies to PLLs 0-2.

Symbol	Bit range	R/W	Description
M_MSB	1-0	RW	M high bits

6.3.126. PLLx_P

PLL pre-divider (P) value.

Applies to PLLs 0-3.

Symbol	Bit range	R/W	Description
P	5-0	RW	P parameter value

6.3.127. PLLx_S

PLL post-scaler (S) value.

Applies to PLLs 0-3.

Symbol	Bit range	R/W	Description
S	2-0	RW	S parameter value

6.3.128. PLLx_CNTRL

PLL control register.

Applies to PLLs 0-3.

Symbol	Bit range	R/W	Description
VSEL	6	RW	Voltage selection?
LOCK_EN	5	RW	Lock something? PLL registers maybe?
BYPASS	4	RW	Bypass PLL and use Fref as Fout
RESET	0	RW	0: Leave reset state 1: Put in reset state. If BYPASS is set, Fout still outputs Fref.

6.3.129. PLLx_TEST

PLL test register?

Applies to PLLs 0-3.

6.3.130. PLLx_STATUS

PLL status register.

Applies to PLLs 0-3.

Symbol	Bit range	R/W	Description
LOCK	0	R	Bit set when PLL is locked

6.3.131. PLLx_DIV_CNTRL

PLL additional output divider register.

Applies only to PLL 0 & 1.

Unlike the XXX_CLK_DIV_CNTRL registers, these registers do not suffer from the write-only BYPASS bit bug and can be read directly.

Symbol	Bit range	R/W	Description
BYPASS	7	RW	Enable/disable divider bypass. 0=apply divider, 1=bypass
?	6	?	Unknown
DIVIDER	0-4	RW	Clock divider value.

7. Real Time Clock

The RTC IP block used in the C2000 is an improved revision of the one used in Samsung S3C2410 and S3C2412 SoCs (and maybe others in the S3C series). The S3C variants contain an additional clock divider, store the year with only 2 digits, and lack the day of week alarm information.

In order to work, the RTC block requires the RTC_XI and RTC_XO pads to be connected to a 32768 Hz oscillator. RTC_VDD must also be connected to a 3.3V supply, or to a 3V coin cell battery. If any of these conditions is not met, the RTC counters will not run.

7.1. Register access

The core APB typically runs at 250 MHz, whereas the RTC APB runs at 50 MHz. Because of this, access is performed via a "proxy" interface.

Also, a delay needs to be inserted between two APB requests, otherwise the transaction gets dropped.

Write access:

Perform a 32 bit write into the register. The lower 16 bits contain the value to write, the upper 16 bits must all be 0.
Wait for 5 microseconds. It is more than is strictly necessary, but this is the amount the Linux driver uses.

Read access:

Write the 32 bit value 0x00010000 into the register you want to read. No actual write occurs to the RTC registers, it is just a way to tell the APB/RTC interface that we want to read the value from that register.
Wait for 5 microseconds.
Read the value from the register (or any RTC register, really) using a 32 bit access. If bit 16 is not set, you read a stale value from a previous read operation; perform another read until bit 16 is set.
The value of the RTC register is the lower 16 bits of the value read in the previous step. Bit 16 must be set, but is not part of the value.

7.2. Registers

Base address	0x904e0000

Interrupt name	GIC SPI
RTC ALM	62
RTC PRI	63

Symbol	Offset	Description
RTCCON	0x00	RTC control register
RTCALM	0x04	RTC alarm control register
ALMSEC	0x08	Alarm second data register
ALMMIN	0x0c	Alarm minute data register
ALMHOUR	0x10	Alarm hour data register
ALMDATE	0x14	Alarm date data register
ALMDAY	0x18	Alarm day of week data register
ALMMON	0x1c	Alarm month data register
ALMYEAR	0x20	Alarm year data register
BCDSEC	0x24	BCD second register
BCDMIN	0x28	BCD minute register
BCDHOUR	0x2c	BCD hour register
BCDDATE	0x30	BCD date register
BCDDAY	0x34	BCD day register
BCDMON	0x38	BCD month register
BCDYEAR	0x3c	BCD year register
RTCIM	0x40	RTC interrupt mode register
RTCPEND	0x44	RTC interrupt pending register

7.2.1. RTCCON (0x904e0000)

RTC control register.

Reset value: 0x00

Symbol	Bit range	R/W	Description
reserved	15-4	R	Reserved. Must be 0.
?	3	RW	Unkonwn
CLKRST	2	RW	RTC clock count reset. Purpose unknown.
RTCEN	1	RW	RTC write enable. Used to prevent accidental writes to the date/time. 0=Read-only 1=Write enabled
STARTB	0	RW	RTC halt. Halts the clock counter. Useful when setting the date/time. 0=Counters are running 1=Counters are halted

7.2.2. RTCALM (0x904e0004)

RTC alarm control register.

Reset value: 0x00

Symbol	Bit range	R/W	Description
reserved	15-8	R	Reserved. Must be 0.
GLOBALEN	7	RW	Alarm global enable.
YEAREN	6	RW	Year alarm enable.
MONEN	5	RW	Month alarm enable.
DAYEN	4	RW	Day alarm enable.
DATEEN	3	RW	Date alarm enable.
HOUREN	2	RW	Hour alarm enable.
MINEN	1	RW	Minute alarm enable.
SECEN	0	RW	Second alarm enable.

7.2.3. ALMSEC (0x904e0008)

Alarm second data register.

Reset value: 0x00

Symbol	Bit range	R/W	Description
reserved	15-7	R	Reserved. Must be 0.
SECDATA	6-0	RW	BCD value for alarm second

7.2.4. ALMMIN (0x904e000c)

Alarm minute data register.

Reset value: 0x00

Symbol	Bit range	R/W	Description
reserved	15-7	R	Reserved. Must be 0.
MINDATA	6-0	RW	BCD value for alarm minute

7.2.5. ALMHOUR (0x904e0010)

Alarm hour data register.

Reset value: 0x00

Symbol	Bit range	R/W	Description
reserved	15-6	R	Reserved. Must be 0.
HOURDATA	5-0	RW	BCD value for alarm hour

7.2.6. ALMDATE (0x904e0014)

Alarm date (day of month) data register.

Reset value: 0x00

Symbol	Bit range	R/W	Description
reserved	15-6	R	Reserved. Must be 0.
DATEDATA	5-0	RW	BCD value for alarm date, from 0 to 28, 29, 30, 31

7.2.7. ALMDAY (0x904e0018)

Alarm day (day of week) data register.

Reset value: 0x00

Symbol	Bit range	R/W	Description
reserved	15-3	R	Reserved. Must be 0.
DAYDATA	2-0	RW	BCD value for alarm day (1-7)

7.2.8. ALMMON (0x904e001c)

Alarm month data register.

Reset value: 0x00

Symbol	Bit range	R/W	Description
reserved	15-5	R	Reserved. Must be 0.
MONTHDATA	4-0	RW	BCD value for alarm month

7.2.9. ALMYEAR (0x904e0020)

Alarm year data register.

Reset value: 0x00

Symbol	Bit range	R/W	Description
YEARDATA	15-0	RW	BCD value for alarm year

7.2.10. BCDSEC (0x904e0024)

BCD second register.

Reset value: 0x00

Symbol	Bit range	R/W	Description
reserved	15-7	R	Reserved. Must be 0.
SECDATA	6-0	RW	BCD value for second

7.2.11. BCDMIN (0x904e0028)

BCD minute register.

Reset value: 0x00

Symbol	Bit range	R/W	Description
reserved	15-7	R	Reserved. Must be 0.
MINDATA	6-0	RW	BCD value for minute

7.2.12. ALMHOUR (0x904e002c)

BCD hour register.

Reset value: 0x00

Symbol	Bit range	R/W	Description
reserved	15-6	R	Reserved. Must be 0.
HOURDATA	5-0	RW	BCD value for hour

7.2.13. BCDDATE (0x904e0030)

BCD date (day of month) register.

Reset value: 0x00

Symbol	Bit range	R/W	Description
reserved	15-6	R	Reserved. Must be 0.
DATEDATA	5-0	RW	BCD value for date, from 0 to 28, 29, 30, 31

7.2.14. BCDDAY (0x904e0034)

BCD day (day of week) register.

Reset value: 0x00

Symbol	Bit range	R/W	Description
reserved	15-3	R	Reserved. Must be 0.
DAYDATA	2-0	RW	BCD value for day (1 to 7)

7.2.15. BCDMON (0x904e0038)

BCD month register.

Reset value: 0x00

Symbol	Bit range	R/W	Description
reserved	15-5	R	Reserved. Must be 0.
MONTHDATA	4-0	RW	BCD value for month

7.2.16. BCDYEAR (0x904e003c)

BCD year register.

Reset value: 0x00

Symbol	Bit range	R/W	Description
YEARDATA	15-0	RW	BCD value for year

7.2.17. RTCIM (0x904e0040)

RTC interrupt mode register.

Reset value: 0x00

Symbol	Bit range	R/W	Description
reserved	15-3	R	Reserved. Must be 0.
?	5-2	RW	Unknown. Might contain periodic tick interrupt control.
?	1	RW	Alarm? interrupt enable? Usually set/unset with ALMEN.
ALMEN	0	RW	Alarm interrupt enable?

7.2.18. RTCPEND (0x904e0044)

RTC interrupt pending register.

When handling an alarm interrupt, disable alarm in RTCALM, disable the interrupt in RTCIM, and write 0 in RTCPEND to acknowledge the interrupt.

Reset value: 0x00

Symbol	Bit range	R/W	Description
?	15-2	RW	Unknown or reserved.
ALMEN?	1	RW	Alarm? global? interrupt enable?
?	0	RW	Alarm interrupt pending? Write 0 to acknowledge.

8. OTP controller

8.1. Registers

Base address		0x904f0000
Size		0x?

Symbol	Offset	Description
CONFIG_LOCK0	0x00	CEB write protect register 0
CONFIG_LOCK1	0x04	CEB write protect register 1
CEB_SEQUENCE_LOCKS	0x08
CEB_INPUT	0x0c	Chip enable input register
RSTB_INPUT	0x10	Reset buffer input register
ADDR_INPUT	0x14	Address input register
READEN_INPUT	0x18	Read enable input register
DATA_INPUT	0x1c	Program data input register
DLE_INPUT	0x20	Data latch enable input register
WEB_INPUT	0x24	Write enable input register
WEB_COUNTER	0x28
PGMEN_INPUT	0x2c	Program enable input register
PGM2CPUMP_COUNTER	0x30
CPUMPEN_INPUT	0x34	Charge pump enable input register
CPUMP2WEB_COUNTER	0x38
WEB2CPUMP_COUNTER	0x3c
CPUMP2PGM_COUNTER	0x40
CLE_INPUT	0x44	Command latch enable input register
SECURE_LOCK_OUTPUT	0x48	Secure lock output register
DATA_OUT_COUNTER	0x4c
DATA_OUTPUT	0x50	Data output register
HW_SEC_MODE_STATUS	0x54	Secure mode status register

8.1.1. CONFIG_LOCK0 (0x904f0000)

OTP CEB write protect lock register 0. Both CONFIG_LOCK0 and CONFIG_LOCK1 registers must contains the correct values to be able to write into the CEB_INPUT register and take the OTP block out of standby.

Symbol	Bit range	R/W	Description
LOCK0	31-0	RW	Unlock write protect. Write 0xebcf0000 to unlock.

8.1.2. CONFIG_LOCK1 (0x904f0004)

OTP CEB write protect lock register 1. Both CONFIG_LOCK0 and CONFIG_LOCK1 registers must contains the correct values to be able to write into the CEB_INPUT register and take the OTP block out of standby.

Symbol	Bit range	R/W	Description
LOCK1	31-0	RW	Unlock write protect. Write 0xebcf1111 to unlock.

8.1.3. CEB_SEQUENCE_LOCKS (0x904f0008)

Unknown.

Symbol	Bit range	R/W	Description

8.1.4. CEB_INPUT (0x904f000c)

Input value for the #CEB signal.

When driven low, OTP block goes out of standby. When driven high, OTP block returns to standby.

Symbol	Bit range	R/W	Description
CEB	0	RW	Value used to drive the #CEB input. 0=low (active) 1=high (standby)

8.1.5. RSTB_INPUT (0x904f0010)

Input value for the #RSTB signal.

#RSTB must be used to reset all command registers and input buffers before entering test mode or normal program mode (do it to even if you only intend to read). #RSTB is ignored in standby mode so #CEB must be low.

#RSTB reset sequence:

write 0 to drive #RSTB low
wait at least 20 ns
write 1 to drive #RSTB high (generate rising edge)
wait at least 1 us

Symbol	Bit range	R/W	Description
RSTB	0	RW	Value used to drive the #RSTB input. 0=low (initiate reset) 1=high (complete reset)

8.1.6. ADDR_INPUT (0x904f0014)

Address input register for read, program and command operations to address individual bits.

The A[13:0] signals take their input directly from this register. A[13] is only used in test mode.

When reading, wait at least 1.5 us before reading the data.

Symbol	Bit range	R/W	Description
ADDR	13-0	RW	Address for read/program/command operations.

8.1.7. READEN_INPUT (0x904f0018)

When READEN is high, the OTP block enters read mode: 8 bits at the address in the ADDR_INPUT are read from the array and output into the DATA_OUTPUT register.

As long as READEN is high, a new address can be written into ADDR_INPUT to perform another read operation.

Symbol	Bit range	R/W	Description
READEN	0	RW	Value used for `READEN`. 0=no read operation 1=start/continue read operation

8.1.8. DATA_INPUT (0x904f001c)

The value written into this register must be latched using the DLE signal.

Symbol	Bit range	R/W	Description
DIN	0	RW	Value used for `DIN`. 0=bit will keep its current value 1=bit will be programmed as 1

8.1.9. DLE_INPUT (0x904f0020)

The DLE signal is used to latch the input data bit (DIN) into the input buffer for the programming sequence.

Symbol	Bit range	R/W	Description
DLE	0	RW	Value used for `DLE`. 0=no change 1=latch data bit into the input buffer

8.1.10. WEB_INPUT (0x904f0024)

A negative WEB pulse is used to initiate a program data sequence.

Symbol	Bit range	R/W	Description
WEB	0	RW	Value used for `WEB`. 0=initiate write operation 1=idle state

8.1.11. WEB_COUNTER (0x904f0028)

Counter values for the WEB signal.

Symbol	Bit range	R/W	Description
?_COUNTER	31-16	W?	? (Typical value: 0x07d0)
?_COUNTER	15-0	RW	? (Typical value: 0x07d0)

8.1.12. PGMEN_INPUT (0x904f002c)

Driving PGMEN high will initiate a program cycle using timings specified in the various counter registers. The CPUMPEN signal will be handled automatically.

When the programming sequence is complete, PGMEN is deasserted automatically.

Symbol	Bit range	R/W	Description
PGMEN	0	RW	Value used for `PGMEN`. 0=keep high voltage circuit off 1=enable high voltage circuit and trigger programming sequence

8.1.13. PGM2CPUMP_COUNTER (0x904f0030)

PGM -> CPUMP state transition counter register?

Counter register used to time the programming sequence.

Symbol	Bit range	R/W	Description
?_COUNTER	31-16	W?	? (Typical value: 0x0190)
?_COUNTER	15-0	RW	? (Typical value: 0x0190)

8.1.14. CPUMPEN_INPUT (0x904f0034)

When CPUMPEN is high, enable the internal charge pump, or let the external Vpp voltage used for programming through. Only set when programming.

When CPUMPEN is low, charge pump is disabled/Vpp voltage is blocked.

When the OTP program sequence is initiated using the PGMEN_INPUT register, the CPUMPEN signal is controlled automatically.

Symbol	Bit range	R/W	Description
CPUMPEN	0	RW	Value used for `PGMEN`. 0=keep high voltage circuit off 1=enable high voltage circuit and trigger programming sequence

8.1.15. CPUMP2WEB_COUNTER (0x904f0038)

CPUMP -> WEB state transition counter register?

Counter register used to time the programming sequence.

Symbol	Bit range	R/W	Description
?_COUNTER	31-16	W?	? (Typical value: 0x04b0)
?_COUNTER	15-0	RW	? (Typical value: 0x04b0)

8.1.16. WEB2CPUMP_COUNTER (0x904f003c)

WEB -> CPUMP state transition counter register?

Counter register used to time the programming sequence.

Symbol	Bit range	R/W	Description
?_COUNTER	31-16	W?	? (Typical value: 0x0320)
?_COUNTER	15-0	RW	? (Typical value: 0x0320)

8.1.17. CPUMP2PGM_COUNTER (0x904f0040)

CPUMP -> PGM state transition counter register?

Counter register used to time the programming sequence.

Symbol	Bit range	R/W	Description
?_COUNTER	31-16	W?	? (Typical value: 0x0190)
?_COUNTER	15-0	RW	? (Typical value: 0x0190)

8.1.18. CLE_INPUT (0x904f0044)

The CLE (Command Latch Enable) allows entering command/test mode.

Symbol	Bit range	R/W	Description
CLE	0	RW	0=do nothing 1=latch and process command from ADDR_INPUT

8.1.19. SECURE_LOCK_OUTPUT (0x904f0048)

Secure lock output status register.

OTP array is read/write as long as the security lock is disabled.

Once the security lock is enabled, the OTP becomes permanently read-only.

Symbol	Bit range	R/W	Description
LOCK	0	R	0=security lock disabled, OTP is read/write 1=security lock enabled, OTP is permanently read-only

8.1.20. DATA_OUT_COUNTER (0x904f004c)

Symbol	Bit range	R/W	Description
?_COUNTER	?-0	RW	? (Typical value: 0x1c)

8.1.21. DATA_OUTPUT (0x904f0050)

Symbol	Bit range	R/W	Description
DATA	7-0	RW	Data read from OTP array after read operation

8.1.22. HW_SEC_MODE_STATUS (0x904f0054)

Symbol	Bit range	R/W	Description
?	8	R	?
SEC_MODE	7-0	R	First byte of data from OTP

9. Timers

6 general purpose timers
6 PWM timers
- Each PWM can drive one output pin
- Independently configurable period and duty cycle
One 16 bit TDM frame sync timer
- incremented on Tx frame SYNC or Rx frame SYNC
- interrupt on one or both of the 2 timer pulses
One 32 bit watchdog timer
- performs a hard reset of the system if the CPU does not reset the timer count before it reaches its maximum value

9.1. General purpose timers

9.1.1. Features

Six 32 bit timers
timers can generate interrupts on timeout pulse
timers can be paired (chained) to form 64 bit timers
timers 2, 3 & 5 have programmable low and high bounds, the others have their lower bound hardcoded to 0.
timers 0, 1 & 4 do not have a low bound, but can be reloaded with a specific count value
timer 1 (resp. 4) can count external events on pin TIM_EVNT0 (resp. TIM_EVNT1) when that pin is configured as an input.
timer 3 (resp. 5) can drive TIM_EVNT0 (resp. TIM_EVNT1) and switch its logical state when the counter reaches the high bound.

9.1.2. Operation in normal mode

In normal mode, all the timers are free-running counters which are incremented on the rising edge of HCLK.

The counter value is reset to its lower bound (or zero for timers 0, 1 & 4) when one of its bound is written. It is therefore recommended for timers 2, 3 & 5 to set the lower bound last.

When the counter equals the high bound value, the timer output is asserted and, if the corresponding bit is set in the TIMER_IRQ_MASK register, an interrupt pulse is generated. Then, on the next rising edge of HCLK, the counter value is reset to the lower bound value.

For timer 3 (resp. 5), the logical state of the TIM_EVNT0 (resp. TIM_EVNT1) output is also toggled when the counter value is equal to the high bound value. (It may requires a flag to be set in the control register to work.)

9.1.3. Event counter mode (timers 1 & 4 only)

Timers 1 (resp. 4) can count events occurring on TIM_EVNT0 (resp. TIM_EVNT1). It requires TIM_EVNTx to be configured as input, and the bit ??? in TIMERx_CTRL to be set.

The counter is incremented on every rising or falling edge on TIM_EVNTx. The pulse must be held for at least 1 HCLK cycle + 3 ns for the edge to be detected.

How to choose between rising or falling edge or both is still unclear.

9.1.4. Operation in chained mode

Timers can be paired to operate in chained mode, effectively turning two 32 bit timers into a single 64 bit timer. In this mode, the low order timer of the pair is running as usual, while the high order one is incremented only when the low order timer times out.

The table below lists all possible timer pairs.

Low order	High order
Timer 0	Timer 2
Timer 1	Timer 3
Timer 4	Timer 5

Chaining mode can be enabled by writing the bit 0 (CHAIN) in TIMERx_CTRL of the high order timer.

9.1.5. Registers

Base address	0x90450000

Interrupt name	GIC SPI
TIMER0	55 (pulse)
TIMER1	56 (pulse)
TIMER2	57 (pulse)
TIMER3	58 (pulse)
TIMER4	59 (pulse)
TIMER5	60 (pulse)

9.1.5.1. TIMERx_LOW_BOUND

Symbol	Address
TIMER2_LOW_BOUND	0x90450010
TIMER3_LOW_BOUND	0x90450020
TIMER5_LOW_BOUND	0x90450038

Low bound value for the timer. It is reloaded automatically into the counter when the cycle after it reaches the high bound.

Symbol	Bit range	R/W	Description
LOW_BOUND	31-0	RW	Timer counter low bound. When written, reset the current counter to that value.

9.1.5.2. TIMERx_HIGH_BOUND

Symbol	Address
TIMER0_HIGH_BOUND	0x90450000
TIMER1_HIGH_BOUND	0x90450008
TIMER2_HIGH_BOUND	0x90450014
TIMER3_HIGH_BOUND	0x90450024
TIMER4_HIGH_BOUND	0x90450030
TIMER5_HIGH_BOUND	0x9045003c

High bound value for the timer. When the counter reaches this value, its output is asserted.

Symbol	Bit range	R/W	Description
HIGH_BOUND	31-0	RW	Timer counter high bound. Reset counter to low bound when written.

9.1.5.3. TIMERx_CURRENT_COUNT

Symbol	Address
TIMER0_CURRENT_COUNT	0x90450004
TIMER1_CURRENT_COUNT	0x9045000c
TIMER2_CURRENT_COUNT	0x9045001c
TIMER3_CURRENT_COUNT	0x9045002c
TIMER4_CURRENT_COUNT	0x90450034
TIMER5_CURRENT_COUNT	0x90450040

Current counter value for the timer.

Symbol	Bit range	R/W	Description
CURRENT_COUNT	31-0	RW?	Current counter value. Can be set for at least timers 0, 1 & 4.

9.1.5.4. TIMERx_CTRL

Symbol	Address
TIMER2_CTRL	0x90450018
TIMER3_CTRL	0x90450028
TIMER5_CTRL	0x90450044

Control register for the timer.

Symbol	Bit range	R/W	Description
reserved	31-1	R	Reserved. Must be 0.
CHAIN	0	RW	Increment counter on another timer output rising edge instead of HCLK

9.1.5.5. TIMER_IRQ_MASK (0x90450048)

Timer interrupt mask register.

Set the bit corresponding to the timer you want to enable interrupts for. Reset the bit to disable interrupts for that timer.

Symbol	Bit range	R/W	Description
TIMER5	5	RW	Timer 5 interupt mask. 0=masked 1=unmasked
TIMER4	4	RW	Timer 4 interupt mask. 0=masked 1=unmasked
TIMER3	3	RW	Timer 3 interupt mask. 0=masked 1=unmasked
TIMER2	2	RW	Timer 2 interupt mask. 0=masked 1=unmasked
TIMER1	1	RW	Timer 1 interupt mask. 0=masked 1=unmasked
TIMER0	0	RW	Timer 0 interupt mask. 0=masked 1=unmasked

9.1.5.6. TIMER_STATUS (0x90450050)

Timer completion status register.

For each timer, the corrsponding bit in this register shows whether that timer reached its high bound value since the last time its status bit was cleared.

Symbol	Bit range	R/W	Description
TIMER5	5	R	Timer 5 status. 0=hasn't completed yet 1=completed at least once
TIMER4	4	R	Timer 4 status. 0=hasn't completed yet 1=completed at least once
TIMER3	3	R	Timer 3 status. 0=hasn't completed yet 1=completed at least once
TIMER2	2	R	Timer 2 status. 0=hasn't completed yet 1=completed at least once
TIMER1	1	R	Timer 1 status. 0=hasn't completed yet 1=completed at least once
TIMER0	0	R	Timer 0 status. 0=hasn't completed yet 1=completed at least once

9.1.5.7. TIMER_STATUS_CLR (0x90450050)

Timer completion status clear register.

When a timer has completed, its status bit can be reset by writing 1 in this bit.

Symbol	Bit range	R/W	Description
TIMER5	5	W	Write 1 to clear timer 5 completion status.
TIMER4	4	W	Write 1 to clear timer 4 completion status.
TIMER3	3	W	Write 1 to clear timer 3 completion status.
TIMER2	2	W	Write 1 to clear timer 2 completion status.
TIMER1	1	W	Write 1 to clear timer 1 completion status.
TIMER0	0	W	Write 1 to clear timer 0 completion status.

9.2. PWM timers

9.2.1. Features

6 PWM outputs muxed with GPIO
PWM module is clocked with AHB/APB clock
A global divider can be used to divide the clock rate for all the PWMs
Each PWM period and duty cycle can be programmed independently

9.2.2. Operation

The PWM timer is a counter which is incremented on every pulse from the output of the global PWM clock divider (which can be disabled).

The counter starts counting from 0, and the PWM output is 0. When the counter reaches the programmable LOW_DUTY_CYCLE value, the PWM output becomes 1. After the counter reaches the programmable MAX_DUTY_CYCLE value, it is reset to zero and the PWM output is reset to 0.

If the PWM timer is disabled, the PWM output is 0.

If the clock divider registers or the duty cycle registers are written, the PWM counter is reset to 0, as well as the PWM output.

9.2.3. Registers

Base address	0x9045????

9.2.3.1. PWM_DIVCTRL (0x9045???? + 0x00)

Register controlling the global PWM clock divider. When enabled, it divides the input AHB/APB clock by the specified ratio.

Symbol	Bit range	R/W	Description
ENABLE	31	RW	Enable the clock divider
DIV	7-0	RW	Divider ratio. Actual divider is DIV + 1. To divide by 1, disable the divider.

9.2.3.2. PWMx_DUTY_CYCLE (0x9045????)

PWM0_DUTY_CYCLE	0x9045????
PWM1_DUTY_CYCLE	0x9045????
PWM2_DUTY_CYCLE	0x9045????
PWM3_DUTY_CYCLE	0x9045????
PWM4_DUTY_CYCLE	0x9045????
PWM5_DUTY_CYCLE	0x9045????

Thresholds defining the behaviour of the PWM timer.

Symbol	Bit range	R/W	Description
LOW_DUTY_CYCLE	?	RW	Low duty cycle value
MAX_DUTY_CYCLE	?	RW	Max duty cycle value

9.3. Watchdog timer

The LS1024A features a 32 bit watchdog counter, which can reset the system if the counter value is not reset before it reaches its programmable limit.

The watchdog timer is similar to the other low-order timers: it is a free-running 32 bit counter, driven by the AHB clock (usually 250 MHz).

Unlike the regular timers, the watchdog counter is not reset when it reaches the HIGH_BOUND value.

Also note that the watchdog only triggers a reset when the counter value is equal to the HIGH_BOUND value; no reset will occur while the counter is above HIGH_BOUND.

For the system to actually reset on watchdog timer overflow, the AXI_WD_RST_EN bit must be set in the DEVICE_RST_CNTRL register.

9.3.1. Registers

Symbol	Offset	Description
HIGH_BOUND	0xd0	Watchdog max count register
CONTROL	0xd4	Watchdog control register
CURRENT_COUNT	0xd8	Watchdog current count register

9.3.1.1. HIGH_BOUND (0x904500d0)

Maximum value for the watchdog counter at which to perform a system reset. Writing a new value resets CURRENT_COUNT.

Symbol	Bit range	R/W	Description
HIGH_BOUND	31-0	RW	Maximum counter value

9.3.1.2. CONTROL (0x904500d4)

Watchdog timer control register. Can enable or disable the watchdog timer.

Disabling the watchdog does not cause the watchdog timer to stop counting, but only prevents it from requesting a system reset.

Symbol	Bit range	R/W	Description
reserved	31-1	R	Reserved. Must be 0.
ENABLE	0	RW	Enable the watchdog reset timer. 0=disable 1=enable

9.3.1.3. CURRENT_COUNT (0x904500d8)

Watchdog timer current count.

Symbol	Bit range	R/W	Description
CURRENT_COUNT	31-0	RW	Read or set the current watchdog timer counter.

10. PCI Express controller

The LS1024A features a PCI Express controller. It is a Synopsys Designware IP used in many SoC designs. The documentation is not publicly available from Synopsys, however the publicly available QorIQ LS1012A Reference Manual contains a full register documentation. Some details may vary depending on the configuration options selected by the SoC manufacturer, but the register offsets within the controller MMIO regions should be identical (the MMIO regions base offsets may differ though).

11. PCIe, SATA and USB control

Configuration registers for PCIe, SATA and USB 2.0 Designware IPs.

11.1. Registers

Base address	0x90460000

Symbol	Offset	Description
PCIE0_CFG0	0x000	PCIE0 configuration register 0
PCIE0_CFG1	0x004	PCIE0 configuration register 1
PCIE0_CFG2	0x008	PCIE0 configuration register 2
PCIE0_CFG3	0x00c	PCIE0 configuration register 3
PCIE0_CFG4	0x010	PCIE0 configuration register 4
PCIE0_CFG5	0x014	PCIE0 configuration register 5
PCIE0_CFG6	0x018	PCIE0 configuration register 6
PCIE1_CFG0	0x020	PCIE1 configuration register 0
PCIE1_CFG1	0x024	PCIE1 configuration register 1
PCIE1_CFG2	0x028	PCIE1 configuration register 2
PCIE1_CFG3	0x02c	PCIE1 configuration register 3
PCIE1_CFG4	0x030	PCIE1 configuration register 4
PCIE1_CFG5	0x034	PCIE1 configuration register 5
PCIE1_CFG6	0x038	PCIE1 configuration register 6
USB0_DWC_CFG_REGF	0x03c	DWC USB 2.0 controller configuration register
PCIE0_STS0	0x040	PCIE0 status register 0
PCIE0_STS1	0x044	PCIE0 status register 1
PCIE0_STS2	0x048	PCIE0 status register 2
PCIE1_STS0	0x04c	PCIE1 status register 0
PCIE1_STS1	0x050	PCIE1 status register 1
PCIE1_STS2	0x054	PCIE1 status register 2
PCIE0_STS3	0x058	PCIE0 status register 3
PCIE1_STS3	0x05c	PCIE1 status register 3
PCIE0_PWR_CFG_BDGT_DATA	0x080	PCIE0 power budgeting configuration data?
PCIE0_PWR_CFG_BDGT_FN	0x084	PCIE0 power budgeting configuration function?
PCIE1_PWR_CFG_BDGT_DATA	0x088	PCIE1 power budgeting configuration data
PCIE1_PWR_CFG_BDGT_FN	0x08c	PCIE1 power budgeting configuration function?
PCIE0_RADM_STS	0x0c0	PCIE0 RADM status register?
PCIE0_PWR_STS_BDGT	0x0c4	PCIE0 power budgeting status register?
PCIE1_RADM_STS	0x0c8	PCIE1 RADM status register?
PCIE1_PWR_STS_BDGT	0x0cc	PCIE1 power budgeting status register?
PCIE0_INTR_STS	0x100	PCIE0 interrupt status register
PCIE0_INTR_EN	0x104	PCIE0 interrupt enable register
PCIE0_INTR_MSI_STS	0x108	PCIE0 MSI status register
PCIE0_INTR_MSI_EN	0x10c	PCIE0 MSI enable register
PCIE1_INTR_STS	0x110	PCIE1 interrupt status register
PCIE1_INTR_EN	0x114	PCIE1 interrupt enable register
PCIE1_INTR_MSI_STS	0x118	PCIE1 MSI status register
PCIE1_INTR_MSI_EN	0x11c	PCIE1 MSI enable register

11.1.0.1. PCIEx_CFG0 (0x904600x0)

PCIE0_CFG0	0x90460000
PCIE1_CFG0	0x90460020

PCIEx configuration register 0.

Symbol	Bit range	R/W	Description
DEV_TYPE	4-0	RW	PCIE device type.

Device types:

DEV_TYPE_EP (Endpoint)	0x0
DEV_TYPE_LEP (Legacy endpoint)	0x1
DEV_TYPE_RC (Root Complex)	0x4
DEV_TYPE_UP_SW (Upstream switch port)	0x5
DEV_TYPE_DWN_SW (Downstream switch port)	0x6

11.1.0.2. PCIEx_CFG5 (0x904600x4)

PCIE0_CFG5	0x90460014
PCIE1_CFG5	0x90460034

PCIEx configuration register 5.

Symbol	Bit range	R/W	Description
LINK_DOWN_RST	9	RW	Initiate linkdown reset (I assume it resets LTSSM to link down state)
APP_RDY_L23	2	RW	Delay entry to the L2/L3 Ready state until this bit is set to 1.
LTSSM_ENABLE	1	RW	Enable or disable LTSSM. Setting to 0 causes LTSSM to reset and stay in the Detect state. Set to 1 after configuring the PCIe core registers to resume the LTSSM state machine.
APP_INIT_RST	0	RW	?

11.1.0.3. PCIEx_STS0 (0x9046004x)

PCIE0_STS0	0x90460040
PCIE1_STS0	0x9046004c

PCIEx status register 0.

Symbol	Bit range	R/W	Description
RDLH_LINK_UP	16	R	Data link is up.
XMLH_LINK_UP	15	R	PHY link is up.
LINK_REQ_RST_NOT	0	R	Notify that the link went down unexpectedly and requires a reset (using LINK_DOWN_RST bit in PCIEx_CFG5)? ? 0=requires reset? 1=no action required?

11.1.0.4. PCIEx_INTR_STS (0x904601x0)

PCIE0_CFG0	0x90460100
PCIE1_CFG0	0x90460110

PCIEx interrupt status register.

Pending interrupts have their corresponding bit set when reading. Writing a 1 for an interrupt bit clears that bit.

Symbol	Bit range	R/W	Description
MSI	12	RW	MSI interrupt
LINK_AUTO_BW	11	RW
HP	10	RW
PME	9	RW
AER	8	RW
INTD_DEASSERT	7	RW	Legacy INTD deasserted
INTD_ASSERT	6	RW	Legacy INTD asserted
INTC_DEASSERT	5	RW	Legacy INTC deasserted
INTC_ASSERT	4	RW	Legacy INTC asserted
INTB_DEASSERT	3	RW	Legacy INTB deasserted
INTB_ASSERT	2	RW	Legacy INTB asserted
INTA_DEASSERT	1	RW	Legacy INTA deasserted
INTA_ASSERT	0	RW	Legacy INTA asserted

11.1.0.5. PCIEx_INTR_EN (0x904601x4)

PCIE0_CFG0	0x90460104
PCIE1_CFG0	0x90460114

PCIEx interrupt enable register.

Writing a 1 bit enables the corresponding interrupt, writing a 0 bit disables it.

Symbol	Bit range	R/W	Description
MSI	12	RW	MSI interrupt
LINK_AUTO_BW	11	RW
HP	10	RW
PME	9	RW
AER	8	RW
INTD_DEASSERT	7	RW	Legacy INTD deasserted
INTD_ASSERT	6	RW	Legacy INTD asserted
INTC_DEASSERT	5	RW	Legacy INTC deasserted
INTC_ASSERT	4	RW	Legacy INTC asserted
INTB_DEASSERT	3	RW	Legacy INTB deasserted
INTB_ASSERT	2	RW	Legacy INTB asserted
INTA_DEASSERT	1	RW	Legacy INTA deasserted
INTA_ASSERT	0	RW	Legacy INTA asserted

11.1.0.6. USB0_DWC_CFG_REGF (0x9046003c)

Symbol	Bit range	R/W	Description
usb0_?	12	RW	Force UTMI+ OTG idDig value? Set to 1 for host mode.
usb1_id_sel	9	RW	Selects ID value from register for usb1 (USB 3.0)
usb0_id_sel	8	RW	Selects ID value from register for usb0 (USB 2.0). Set to 1 for host mode.
usb1_scaledown_mode	3-2	RW	Scale-down mode (simulation use). 0 = disabled, other = reserved, to speed up design simulation only (use scaled-down values for timers)
usb0_scaledown_mode	1-0	RW	Scale-down mode (simulation use). 0 = disabled, other = reserved, to speed up design simulation only (use scaled-down values for timers)

12. USB 3.0 PHY

The C2000 has a built-in USB 3.0 PHY, which complies with the PIPE (PHY Interface for PCI Express (and USB 3.0 Architectures)) specification.

The USB 3.0 PHY is connected to the USB1 controller (DWC3_USB) via a PIPE interface featuring a 32-bit data bus. If all the 32 lines are used, the PHY must generate a PIPE clock (PCLK) of 125 MHz.

The reference clock for the USB 3.0 PHY can be generated internally by a PLL, using the 24/48 MHz crystal as reference.

12.1. Registers

Base address	0x904a0000
DWC3_CTRL_REG0	0x904a0010
DWC3_CTRL_REG1	0x904a0014
DWC3_CTRL_REG2	0x904a0018
PHY_CTRL_REG0	0x904a0020
PHY_CTRL_REG1	0x904a0024
PHY_CTRL_REG2	0x904a0028
PHY_CTRL_REG3	0x904a002c

12.1.0.1. DWC3_CTRL_REG0 (0x904a0010)

USB 3.0 controller control register 0.

Symbol	Bit range	R/W	Description
reserved	31-24	?	Reserved. Must be 0.
xhc_bme	23	RW	0=Bus mastering capability disabled 1=Bus mastering capability enabled
xhsi_rev	22	?	1=This XHCI is compliant to xHCI standard revision 1.0 0=?
fladj_30mhz_reg	21-16	RW	Unknown (filter adjust?). Should be set to 32.
bus_filter_bypass	15-12	RW	b'0000=Bus filters enabled b'1111=Bus filters bypassed
reserved	11-10	?	Reserved. Must be 0.
pme_en	9	RW	0=Disable the PME generation 1=Enable the PME generation
host_port_power_control_present	8	RW	0=Port does not have power switched 1=Port has power switches
vbus_ctrl_en	7	RW	0=(device) do not allow controller to drive PHY's DRVVBUS 1=(host) allow controller to drive the PHY's DRVVBUS
host_u3_port_disable	6	RW	0=USB 3.0 port enabled 1=USB 3.0 port disabled
host_u2_port_disable	5	RW	0=USB 2.0 port enabled 1=USB 2.0 port disabled
host_msi_enable	4	RW	0=enable level type interrupt from controller 1=enable pulse type interrupt from controller
hub_port_perm_attach	3-2	RW	b'00=Device is not permanently attached b'11=Device is permanently attached
hub_port_overcurrent	1-0	R?	b'00=No over-current b'11=Over-current

12.1.0.2. DWC3_CTRL_REG1 (0x904a0014)

USB 3.0 controller control register 1.

Symbol	Bit range	R/W	Description
reserved	31-9	?	Reserved.
host_legacy_smi_bar_wr	8	?	?
reserved	7-5	?	Reserved.
host_legacy_smi_pci_cmd_writel	4	R	?
reserved	3-2	?	Reserved.
pm_power_state_request	1-0	RW	?

12.1.0.3. DWC3_CTRL_REG2 (0x904a0018)

USB 3.0 controller control register 2.

Symbol	Bit range	R/W	Description
reserved	31-1	?	Reserved. Must be 0.
light_reset_n	0	RW	Active low reset. Is is similar to the xHCI "Light Reset" which does not reset any sticky bits. When operating as a device, this bit should be kept high. Default=0

12.1.0.4. PHY_CTRL_REG0 (0x904a0020)

USB 3.0 PHY control register 0.

Symbol	Bit range	R/W	Description
ssc_reg_clk_sel	31-23	RW	Spread Spectrum Reference Clock Shifting. Recommended value: 0100_0010_0
ssc_range	22-20	RW	Spread Spectrum Clock Range
ssc_en	19	RW	Spead Spectrum Enable
mpll_multiplier	18-12	RW	MPLL Frequency Multiplier Control, but only relevant is refclksel=b'11
commononn	11	RW	Common Block Power-Down Control. 0=off? 1=on?
ref_clkdiv2	10	RW	Input Reference Clock Divider Control
fsel	9-4	RW	Frequency select.
refclksel	3-2	RW	Input Reference Select for HS PLL Block.
ref_use_pad	1	RW	Select external reference clock. Usually b'10
phy_sel_div2_clk	0	RW	Divide reference clock by 2. 0=bypass divider 1=divide by 2

12.1.0.5. PHY_CTRL_REG1 (0x904a0024)

USB 3.0 PHY control register 1.

Symbol	Bit range	R/W	Description
sqrxtune0	31-29	RW	Recommended value: b'011
los_level	28-24	RW	Recommended value: b'0_1001
ref_ssp_en	23	RW	Recommended value: b'1
otgtune0	22-20	RW	Recommended value: b'100
txfslstune0	19-16	RW	Recommended value: b'100
txpreemppulsetune0	15	RW	Recommended value: b'0
compdistune0	14-12	RW	Recommended value: b'100
txpreempamptune0	11-10	RW	Recommended value: b'11
txhsxvtune0	9-8	RW	Recommended value: b'11
txrestune0	7-6	RW	Recommended value: b'01
txrisetune0	5-4	RW	Recommended value: b'01
txvreftune0	3-0	RW	Recommended value: b'0011

12.1.0.6. PHY_CTRL_REG2 (0x904a0028)

USB 3.0 PHY control register 2.

Symbol	Bit range	R/W	Description
lane0_tx_term_offset	31-27	RW	Recommended value: b'0_0000
reserved	26	?	Reserved. Must be 0.
tx_vboost_lvl	25-23	RW	Recommended value: b'000
lod_bias	22-20	RW	Recommended value: b'000
vbusvldextsel0	19	RW	Recommended value: b'0
pcs_tx_swing_full	18-12	RW	Recommended value: b'101_1101
pcs_tx_deemph_6db	11-6	RW	Recommended value: b'10_0000
pcs_tx_deemph_3p5db	5-0	RW	Recommended value: b'01_0101

12.1.0.7. PHY_CTRL_REG3 (0x904a002c)

USB 3.0 PHY control register 3.

Symbol	Bit range	R/W	Description
reserved	31-17	?	Reserved. Must be 0.
loopbackenb0	16	RW	0=Loopback disabled (default) 1=Loopback enabled
adpprbenb0	15	RW	Recommended value: b'0
adbdischrg0	14	RW	Recommended value: b'0
adbchrg0	13	RW	Recommended value: b'0
idpullup0	12	RW	Recommended value: b'0 if host-only
drvvbus0	11	RW	Recommended value: b'1 if host-only
vbusvldext0	10	RW	Recommended value: b'0
vatestenb	9-8	RW	Recommended value: b'00
otgdisable	7	RW	Recommended value: b'0
test_powerdown_ssp	6	RW	Recommended value: b'0
test_powerdown_hsp	5	RW	Recommended value: b'0
lane0_tx2rx_loopbk	4	RW	Recommended value: b'0
lane0_ext_pclk_req	3	RW	Recommended value: b'0
reserved	2-1	?	Reserved. Must be 0.
rerenablen	0	RW	Recommended value: b'1

13. USB PHY and SerDes

USB 2.0 PHY and SerDes configuration and status registers. The status registers collect the status lines coming out of the USB 2.0 PHY and the SerDes PHYs IP blocks. The control registers can set inputs of those PHYs IP blocks.

13.1. Registers

Base address	0x90410000

Symbol	Offset	Description
USB0_PHY_CTRL_REG0	0x0000	USB PHY control register (USB 2.0)
SD0_PHY_STS	0x002c	SerDes 0 PHY status register
SD0_PHY_CTRL1	0x0030	SerDes 0 PHY control register 1
SD0_PHY_CTRL2	0x0034	SerDes 0 PHY control register 2
SD0_PHY_CTRL3	0x0038	SerDes 0 PHY control register 3
SD1_PHY_STS	0x003c	SerDes 1 PHY status register
SD1_PHY_CTRL1	0x0040	SerDes 1 PHY control register 1
SD1_PHY_CTRL2	0x0044	SerDes 1 PHY control register 2
SD1_PHY_CTRL3	0x0048	SerDes 1 PHY control register 3
SD2_PHY_STS	0x004c	SerDes 2 PHY status register
SD2_PHY_CTRL1	0x0050	SerDes 2 PHY control register 1
SD2_PHY_CTRL2	0x0054	SerDes 2 PHY control register 2
SD2_PHY_CTRL3	0x0058	SerDes 2 PHY control register 3

13.1.0.1. USB0_PHY_CTRL_REG0 (0x90410000)

Symbol	Bit range	R/W	Description
usb0_common_disable?	24	RW	Disable common blocks? Saves power. 0 = enabled, 1 = powered down
usb0_refclksel	21-20	RW	Reference clock selsction. 2 = 2.5V clock on XO pin. 0, 1, 3 = ?
usb0_refclkdiv	17-16	RW	Reference clock frequency select. 0 = ?, 1 = 24 MHz, 2 = 48 MHz, 3 = ?
usb0_analog_disable?	6	RW	Disable analog blocks?. Saves power. 0 = enabled, 1 = powered down
usb0_otgdisable	4	RW	Disable OTG block. 0 = enabled, 1 = powered down
usb0_vbusvldext	3	RW	VBUS signal valid. 0 = no, pull-up on D+ disabled, 1 = ?
usb0_vbusvldextsel	2	RW	OTG Session Valid comparator selection. 0 = internal (default), 1 = external (use value from bit 3)

13.1.0.2. SDx_PHY_STS (0x9041002c + (x * 0x10))

Symbol	Bit range	R/W	Description
cmu_ok_o	14	R	CMU is ready
lane_ok_o	12	R	All lanes are ready

13.1.0.3. SDx_PHY_CTRL2 (0x90410034 + (x * 0x10))

Configuration register 2 for SerDes(x) PHY.

Symbol	Bit range	R/W	Description
cmu_rst	16	RW	CMU reset. 0=reset 1=normal operation
cmu_pd	7	RW	0=CMU power up 1=CMU power down
lane_rst	6	RW	Lane reset. 0=reset 1=normal operation
?	3-2	RW	0=nominal 3=low power mode
?	1-0	RW	Clock divider selection? 0=value from CTRL3? 1-3=???

13.1.0.4. SDx_PHY_CTRL3 (0x90410038 + (x * 0x10))

Configuration register 3 for SerDes(x) PHY.

Symbol	Bit range	R/W	Description
ck_soc_div_i	15-0	RW	Clock divider? Reset value: 0x33f Value set by driver: 0xff3c

14. SerDes PHY config

The C2000 SoC features 3x single-lane 5Gbps Snowbush multi-standard SerDes PHY. All the SerDes PHYs can be configured for PCIe, SATA or SGMII, but they do not all have the corresponding controller attached, which effectively limits the number of useful configurations.

The working configurations for each SerDes PHY are:

SerDes PHY	PCIe	SATA	SGMII
SerDes0	X
SerDes1	X	X
SerDes2		X	X

All standards are available when using the internally-generated clock, but this has limitations. To overcome them, external clocks are needed:

Standard	Limitations when using internal clock	External clock frequency
PCIe	Only Gen1 is supported	100 MHz
SATA	No boot from SATA	60 MHz
SGMII	None?	125 MHz

14.1. Memory map

Base address	0x90590000

Range (offset from base)	Region size (w/o mirrors)	Description
0x00000-0x03fff	0x4000	SerDes0 configuration registers
0x04000-0x07fff	0x4000	SerDes1 configuration registers
0x08000-0x0bfff	0x4000	SerDes2 configuration registers

Range in a SerDes block	Region size (w/o mirrors)	Description
0x0000-0x07ff	0x800	Common CMU (Clock Multiplying Unit) registers
0x0800-0x0fff	0x800	Lane 0 registers
0x1000-0x17ff	0x800	Lane 1 registers (unimplemented in this design)
0x1800-0x1fff	0x800	Lane 2 registers (unimplemented in this design)
0x2000-0x27ff	0x800	Lane 3 registers (unimplemented in this design)
0x2800-0x2fff	0x800	Common lane registers

14.2. CMU registers

Symbol	Offset	Description
CMU_CTL?	0x0000	CMU control register

14.2.1. CMUCTL? register

Symbol	Bit range	R/W	Description
ENABLE	0	RW	Enable CMU

14.3. LANE0 registers

Symbol	Offset	Description
CFG0?	0x0000	Unknown
CFG2?	0x0008	Unknown
TX_CFG?	0x001c	Tx line analog config

14.3.1. CFG0? register

Symbol	Bit range	R/W	Description
POLARITY?	3	RW	Invert ??? polarity

14.3.2. CFG2? register

Symbol	Bit range	R/W	Description
POLARITY?	1	RW	Invert ??? polarity

14.3.3. TXCFG register

Symbol	Bit range	R/W	Description
TX_LEV	5-2	RW	Tx level? (0-15)

14.4. Common lanes registers

Symbol	Offset	Description
LANES_CTL?	0x0000	Master lanes control register

14.4.1. LANES_CTL register (0x90592800 + (x * 0x4000))

Symbol	Bit range	R/W	Description
?	7	RW	1 for PCIe operation
?	6	RW	1 for PCIe operation
?	1	RW	Lane0 enable?
?	0	RW	Master lanes enable?

Set to 0xc3 for PCIe, 0x03 for other modes.

15. Packet Forwarding Engine (PFE)

Processor engines (PE):

PE ID	PE name
0	CLASS0
1	CLASS1
2	CLASS2
3	CLASS3
4	CLASS4
5	CLASS5
6	TMU0
7	TMU1
8	TMU2
9	TMU3
10	UTIL

The Class PEs are responsible for classifying packets.

The TMU PEs are responsible for scheduling packets and shaping traffic.

The Util PE is responsible for all the other tasks.

15.1. CBUS (common bus?) memory map

The CBUS is shared by the ARM and all PEs.

Warning: All CBUS accesses from the ARM require the PFE_SYS clock to be running (bit 3 of AXI_CLK_CNTRL_1 set).

Warning: ARM data accesses to the CBUS are byte-swapped on a 4 bytes boundary. That means that reading from 32-bit CBUS registers from the ARM directly returns the value in little-endian byte order. However, this becomes an issue when accessing memories, such as the LMEM, because every group of 4 bytes will be byte-swapped, even on non 32 bit accesses.

Seen from	CBUS base address
ARM	0x9c000000
Any PE	0xc0000000

Base offset in CBUS	Size	Size (w/o mirrors)	Description
0x200000	0x10000	?	EMAC1
0x210000	0x10000	?	EGPI1
0x220000	0x10000	?	EMAC2
0x230000	0x10000	?	EGPI2
0x240000	0x10000	0x800	BMU1
0x250000	0x10000	0x800	BMU2
0x260000	0x10000	?	ARB
0x270000	0x10000	?	DDR_CONFIG
0x280000	0x10000	?	HIF
0x290000	0x10000	?	HGPI
0x300000	0x10000	?	LMEM
0x310000	0x10000	?	TMU_CSR
0x320000	0x10000	?	CLASS_CSR
0x330000	0x10000	?	EMAC3
0x340000	0x10000	?	EGPI3
0x350000	0x10000	?	HIF_NOCPY
0x360000	0x10000	?	UTIL_CSR
0x370000	0x10000	?	CBUS_GPT

Note: Do not attempt to perform a byte access at address 0xffff of a peripheral as it will cause CBUS to hang. Instead, perform a 16-bit access at address 0xfffe.

15.2. Class PE memory map

All addresses are given for the Class PE address space.

Region	Size (w/o mirrors)	Description
0x00000000-0x0000ffff	0x2000	DMEM (per PE data memory)
0x00010000-0x0001ffff	0x8000	PMEM (per PE program memory)
0x00020000-0x85ffffff	?	DDR + ACP + IRAM
0xc0000000-0xc0ffffff	?	CBUS
0xc1000000-0xc1ffffff	?	Class APB bus
0xc2000000-0xc2ffffff	?	Class AHB1 bus
0xc3000000-0xc3ffffff	?	Class AHB2 bus

15.2.1. Class APB bus map

Region	Size (w/o mirrors)	Description
0xc1000000-0xc100ffff	?	GPT (General Purpose Timer)
0xc1010000-0xc101ffff	?	UART
0xc1020000-0xc102ffff	?	PERG
0xc1030000-0xc103ffff	?	EFET

15.2.2. Class AHB1 bus map

Region	Size (w/o mirrors)	Description
0xc2030000-0xc203ffff	?	MAC hash
0xc2050000-0xc205ffff	?	VLAN hash

15.2.3. Class AHB2 bus map

Region	Size (w/o mirrors)	Description
0xc3010000-0xc301ffff	0x8000	PE LMEM
0xc3020000-0xc302ffff	?	CCU

15.3. TMU PE memory map

All addresses are given for the TMU PE address space.

Region	Size (w/o mirrors)	Description
0x00000000-0x0000ffff	0x800	DMEM (per PE data memory)
0x00010000-0x0001ffff	0x2000	PMEM (per PE program memory)
0x00020000-0x85ffffff	?	DDR + ACP + IRAM (not confirmed)
0xc0000000-0xc0ffffff	?	CBUS
0xc1000000-0xc1ffffff	?	TMU APB bus

15.3.1. TMU APB bus map

Region	Size (w/o mirrors)	Description
0xc1000000-0xc100ffff	?	GPT (General Purpose Timer)
0xc1010000-0xc101ffff	?	UART
0xc1020000-0xc102ffff	?	SHAPER0
0xc1030000-0xc103ffff	?	SHAPER1
0xc1040000-0xc104ffff	?	SHAPER2
0xc1050000-0xc105ffff	?	SHAPER3
0xc1060000-0xc106ffff	?	SHAPER4
0xc1070000-0xc107ffff	?	SHAPER5
0xc1080000-0xc108ffff	?	SHAPER6
0xc1090000-0xc109ffff	?	SHAPER7
0xc10a0000-0xc10affff	?	SHAPER8
0xc10b0000-0xc10bffff	?	SHAPER9
0xc11c0000-0xc11cffff	?	SCHED0
0xc11d0000-0xc11dffff	?	SCHED1
0xc11e0000-0xc11effff	?	SCHED2
0xc11f0000-0xc11fffff	?	SCHED3
0xc1200000-0xc120ffff	?	SCHED4
0xc1210000-0xc121ffff	?	SCHED5
0xc1220000-0xc122ffff	?	SCHED6
0xc1230000-0xc123ffff	?	SCHED7
0xc1260000-0xc126ffff	?	PHY_QUEUE
0xc1270000-0xc127ffff	?	SHAPER_STATUS

15.4. Util PE memory map

All addresses are given for the Util PE address space.

Region	Size (w/o mirrors)	Description
0x00000000-0x0000ffff	0x2000	DMEM (per PE data memory)
0x00020000-0x85ffffff	?	DDR + ACP + IRAM
0xc0000000-0xc0ffffff	?	CBUS
0xc1000000-0xc1ffffff	?	Util APB bus

15.4.1. Util APB bus map

Region	Size (w/o mirrors)	Description
0xc1000000-0xc100ffff	?	GPT (General Purpose Timer)
0xc1010000-0xc101ffff	?	UART
0xc1020000-0xc102ffff	?	EAPE
0xc1030000-0xc103ffff	?	INQ
0xc1040000-0xc104ffff	?	EFET1
0xc1050000-0xc105ffff	?	EFET2
0xc1060000-0xc106ffff	?	EFET3

15.5. Ethernet MAC (EMAC)

The EMAC is a Cadence Gigabit Ethernet MAC IP.

The register documentation comes from the Xilinx Zynq-7000 SoC Technical Reference Manual (ug585-Zynq-7000-TRM.pdf).

A driver exist in mainline Linux, but it cannot be used directly with this EMAC implementation as there is no CPU interface.

Each EMAC instance has a matching EGPI block which handles the the Rx and Tx queues. The EGPI blocks make use of the BMU blocks to allocate/free buffers from the buffer pools.

To be able to transmit packets, the 125 MHz gemtx clock must be enabled.

Note: Reading a statistics register will reset its value to 0.

15.5.1. EMAC registers

EMAC instance	Base offset in CBUS
EMAC1	0x200000
EMAC2	0x220000
EMAC3	0x330000

EMAC instance	Associated GPI
EMAC1	EGPI1
EMAC2	EGPI2
EMAC3	EGPI3

Symbol	Offset	Description
NETWORK_CONTROL	0x000	Network control register
NETWORK_CONFIG	0x004	Network config register
NETWORK_STATUS	0x008	Network status register
DMA_CONFIG	0x010	DMA configuration register
TXSR	0x014	Tx status register
RXQBASE	0x018	Rx queue base address (not implemented)
TXQBASE	0x01c	Tx queue base address (not implemented)
RXSR	0x020	Rx status register
ISR	0x024	Interrupt status register
IER	0x028	Interrupt enable register
IDR	0x02c	Interrupt disable register
IMR	0x030	Interrupt mask status register
PHY_MANAGEMENT	0x034	PHY management register
RXPAUSE	0x038	Received pause quantum
TXPAUSE	0x03c	Transmit pause quantum
HASH_BOT	0x080	Hash register bottom
HASH_TOP	0x084	Hash register top
SPEC1_ADD_BOT	0x088	Specific address 1 bottom
SPEC1_ADD_TOP	0x08c	Specific address 1 top
SPEC2_ADD_BOT	0x090	Specific address 2 bottom
SPEC2_ADD_TOP	0x094	Specific address 2 top
SPEC3_ADD_BOT	0x098	Specific address 3 bottom
SPEC3_ADD_TOP	0x09c	Specific address 3 top
SPEC4_ADD_BOT	0x0a0	Specific address 4 bottom
SPEC4_ADD_TOP	0x0a4	Specific address 4 top
MATCH1	0x0a8	Type ID match 1
MATCH2	0x0ac	Type ID match 2
MATCH3	0x0b0	Type ID match 3
MATCH4	0x0b4	Type ID match 4
WOL_ENABLE	0x0b8	Wake on LAN configuration register
STRETCH	0x0bc	IPG stretch register
STACKED_VLAN	0x0c0	Stacked VLAN register
TX_PFC_PAUSE	0x0c4	Transmit PFC pause register
SPEC1_ADD_MASK_BOT	0x0c8	Specific address 1 mask bottom
SPEC1_ADD_MASK_TOP	0x0cc	Specific address 1 mask top
EFTSH	0x0e8	PTP Event Frame Transmitted Seconds Register
EFRSH	0x0ec	PTP Event Frame Received Seconds Register
PEFTSH	0x0f0	PTP Peer Event Frame Transmitted Seconds Register
PEFRSH	0x0f4	PTP Peer Event Frame Received Seconds Register
MODULE_ID	0x0fc	Module ID
OCTETS_TX_BOT	0x100	Octets transmitted 31:0] (in frames without error)
OCTETS_TX_TOP	0x104	Octets transmitted [47:32] (in frames without error)
FRAMES_TX	0x108	Frames transmitted
BROADCAST_TX	0x10c	Broadcast frames Tx
MULTICAST_TX	0x110	Multicast frames Tx
PAUSE_TX	0x114	Pause frames Tx
FRAME64_TX	0x118	Frames Tx, 64-byte length
FRAME65_127_TX	0x11c	Frames Tx, 65 to 127-byte length
FRAME128_255_TX	0x120	Frames Tx, 128 to 255-byte length
FRAME256_511_TX	0x124	Frames Tx, 256 to 511-byte length
FRAME512_1023_TX	0x128	Frames Tx, 512 to 1023-byte length
FRAME1024_1518_TX	0x12c	Frame Tx, 1024 to 1518-byte length
FRAME1519_TX	0x130	Frame Tx, 1519-byte length or more
TX_URUN	0x134	Transmit under runs
SINGLE_COL	0x138	Single collision frames
MULTI_COL	0x13c	Multiple collision frames
EXCESS_COL	0x140	Excessive collisions
LATE_COL	0x144	Late collisions
DEF_TX	0x148	Deferred transmission frames
CRS_ERRORS	0x14c	Carrier sense errors
OCTETS_RX_BOT	0x150	Octets received [31:0]
OCTETS_RX_TOP	0x154	Octets receives [47:32]
FRAMES_RX	0x158	Frames received
BROADCAST_RX	0x15c	Broadcast frames Rx
MULTICAST_RX	0x160	Multicast frames Rx
PAUSE_RX	0x164	Pause frames Rx
FRAME64_RX	0x168	Frames Rx, 64-byte length
FRAME65_127_RX	0x16c	Frames Rx, 65 to 127-byte length
FRAME128_255_RX	0x170	Frames Rx, 128 to 255-byte length
FRAME256_511_RX	0x174	Frames Rx, 256 to 511-byte length
FRAME512_1023_RX	0x178	Frames Rx, 512 to 1023-byte length
FRAME1024_1518_RX	0x17c	Frames Rx, 1024 to 1518-byte length
FRAME1519_RX	0x180	Frames Rx, 1519 byte length or more
USIZE_FRAMES	0x184	Undersize frames received
EXCESS_LENGTH	0x188	Oversize frames received
JABBERS	0x18c	Jabbers received
FCS_ERRORS	0x190	Frame check sequence errors
LENGTH_CHECK_ERRORS	0x194	Length field frame errors
RX_SYMBOL_ERRORS	0x198	Receive symbol errors
ALIGN_ERRORS	0x19c	Alignment errors
RX_RES_ERRORS	0x1a0	Receive resource errors
RX_ORUN	0x1a4	Receive overrun errors
IP_CKSUM	0x1a8	IP header checksum errors
TCP_CKSUM	0x1ac	TCP checksum errors
UDP_CKSUM	0x1b0	UDP checksum error
TISUBN	0x01bc	1588 Timer Increment Sub-ns
TSH	0x01c0	1588 Timer Seconds High
TSL	0x01d0	1588 Timer Seconds Low
TN	0x01d4	1588 Timer Nanoseconds
TA	0x01d8	1588 Timer Adjust
TI	0x01dc	1588 Timer Increment
EFTSL	0x01e0	PTP Event Frame Tx Seconds Low
EFTN	0x01e4	PTP Event Frame Tx Nanoseconds
EFRSL	0x01e8	PTP Event Frame Rx Seconds Low
EFRN	0x01ec	PTP Event Frame Rx Nanoseconds
PEFTSL	0x01f0	PTP Peer Event Frame Tx Secs Low
PEFTN	0x01f4	PTP Peer Event Frame Tx Ns
PEFRSL	0x01f8	PTP Peer Event Frame Rx Sec Low
PEFRN	0x01fc	PTP Peer Event Frame Rx Ns
PCSCNTRL	0x0200	PCS Control
PCSSTS	0x0204	PCS Status
PCSPHYTOPID	0x0208	PCS PHY Top ID
PCSPHYBOTID	0x020c	PCS PHY Bottom ID
PCSANADV	0x0210	PCS AN Advertisement
PCSANLPBASE	0x0214	PCS AN Link Partner Base
PCSANEXP	0x0218	PCS AN Expansion
PCSANNPTX	0x021c	PCS AN Next Page TX
PCSANNPLP	0x0220	PCS AN Next Page LP
PCSANEXTSTS	0x023c	PCS AN Extended Status
DESIGN_CFG1	0x280	Design configuration 1
DESIGN_CFG2	0x284	Design configuration 2
DESIGN_CFG3	0x288	Design configuration 3
DESIGN_CFG4	0x28c	Design configuration 4
DESIGN_CFG5	0x290	Design configuration 5
DESIGN_CFG6	0x294	Design configuration 6
SPEC5_ADD_BOT	0x300	Specific address 5 bottom
SPEC5_ADD_TOP	0x304	Specific address 5 top
SPEC6_ADD_BOT	0x308	Specific address 6 bottom
SPEC6_ADD_TOP	0x30c	Specific address 6 top
SPEC7_ADD_BOT	0x310	Specific address 7 bottom
SPEC7_ADD_TOP	0x314	Specific address 7 top
SPEC8_ADD_BOT	0x318	Specific address 8 bottom
SPEC8_ADD_TOP	0x31c	Specific address 8 top
SPEC9_ADD_BOT	0x320	Specific address 9 bottom
SPEC9_ADD_TOP	0x324	Specific address 9 top
SPEC10_ADD_BOT	0x328	Specific address 10 bottom
SPEC10_ADD_TOP	0x32c	Specific address 10 top
SPEC11_ADD_BOT	0x330	Specific address 11 bottom
SPEC11_ADD_TOP	0x334	Specific address 11 top
SPEC12_ADD_BOT	0x338	Specific address 12 bottom
SPEC12_ADD_TOP	0x33c	Specific address 12 top
SPEC13_ADD_BOT	0x340	Specific address 13 bottom
SPEC13_ADD_TOP	0x344	Specific address 13 top
SPEC14_ADD_BOT	0x348	Specific address 14 bottom
SPEC14_ADD_TOP	0x34c	Specific address 14 top
SPEC15_ADD_BOT	0x350	Specific address 15 bottom
SPEC15_ADD_TOP	0x354	Specific address 15 top
SPEC16_ADD_BOT	0x358	Specific address 16 bottom
SPEC16_ADD_TOP	0x35c	Specific address 16 top
SPEC17_ADD_BOT	0x360	Specific address 17 bottom
SPEC17_ADD_TOP	0x364	Specific address 17 top
SPEC18_ADD_BOT	0x368	Specific address 18 bottom
SPEC18_ADD_TOP	0x36c	Specific address 18 top
SPEC19_ADD_BOT	0x370	Specific address 19 bottom
SPEC19_ADD_TOP	0x374	Specific address 19 top
SPEC20_ADD_BOT	0x378	Specific address 20 bottom
SPEC20_ADD_TOP	0x37c	Specific address 20 top
SPEC21_ADD_BOT	0x380	Specific address 21 bottom
SPEC21_ADD_TOP	0x384	Specific address 21 top
SPEC22_ADD_BOT	0x388	Specific address 22 bottom
SPEC22_ADD_TOP	0x38c	Specific address 22 top
SPEC23_ADD_BOT	0x390	Specific address 23 bottom
SPEC23_ADD_TOP	0x394	Specific address 23 top
SPEC24_ADD_BOT	0x398	Specific address 24 bottom
SPEC24_ADD_TOP	0x39c	Specific address 24 top
SPEC25_ADD_BOT	0x3a0	Specific address 25 bottom
SPEC25_ADD_TOP	0x3a4	Specific address 25 top
SPEC26_ADD_BOT	0x3a8	Specific address 26 bottom
SPEC26_ADD_TOP	0x3ac	Specific address 26 top
SPEC27_ADD_BOT	0x3b0	Specific address 27 bottom
SPEC27_ADD_TOP	0x3b4	Specific address 27 top
SPEC28_ADD_BOT	0x3b8	Specific address 28 bottom
SPEC28_ADD_TOP	0x3bc	Specific address 28 top
SPEC29_ADD_BOT	0x3c0	Specific address 29 bottom
SPEC29_ADD_TOP	0x3c4	Specific address 29 top
SPEC30_ADD_BOT	0x3c8	Specific address 30 bottom
SPEC30_ADD_TOP	0x3cc	Specific address 30 top
SPEC31_ADD_BOT	0x3d0	Specific address 31 bottom
SPEC31_ADD_TOP	0x3d4	Specific address 31 top
SPEC32_ADD_BOT	0x3d8	Specific address 32 bottom
SPEC32_ADD_TOP	0x3dc	Specific address 32 top
CONTROL	0x7a0	EMAC Control register

15.5.1.1. NETWORK_CONTROL (EMAC_BASE + 0x000)

Network control register

The network control register contains general MAC control functions for both receiver and transmitter.

Symbol	Bit range	R/W	Description
reserved	31-19	R	Reserved. Read as zero.
flush_next_rx_dpram_pkt	18	W	Flush the next packet from the external RX DPRAM. Writing one to this bit will only have an effect if the DMA is not currently writing a packet already stored in the DPRAM to memory.
tx_pfc_pri_pri_pause_frame	17	W	Transmit PFC Priority Based Pause Frame. Takes the values stored in the Transmit PFC Pause Register
en_pfc_pri_pause_rx	16	W	Enable PFC Priority Based Pause Reception capabilities. Setting this bit will enable PFC negotiation and recognition of priority based pause frames.
reserved	15	RW	Reserved. Do not modify. Reset value: 0
reserved	14	RW	Reserved. Do not modify. Reset value: 0
reserved	13	W	Reserved. Write as 0
ZEROPAUSETX	12	W	Transmit zero quantum pause frame. Writing one to this bit causes a pause frame with zero quantum to be transmitted.
PAUSETX	11	W	Transmit pause frame - writing one to this bit causes a pause frame to be transmitted.
HALTTX	10	W	Transmit halt - writing one to this bit halts transmission as soon as any ongoing frame transmission ends.
STARTTX	9	W	Start transmission - writing one to this bit starts transmission.
back_pressure	8	RW	Back pressure - if set in 10M or 100M half duplex mode will force collisions on all received frames.
STATWEN	7	RW	Write enable for statistics registers - setting this bit to one means the statistics registers can be written for functional test purposes.
STATINC	6	W	Incremental statistics registers - this bit is write only. Writing a one increments all the statistics registers by one for test purposes.
STATCLR	5	W	Clear statistics registers - this bit is write only. Writing a one clears the statistics registers.
MDEN	4	RW	Management port enable - set to one to enable the management port. When zero forces mdio to high impedance state and mdc low.
TXEN	3	RW	Transmit enable - when set, it enables the GEM transmitter to send data. When reset transmission will stop immediately, the transmit pipeline and control registers will be cleared and the transmit queue pointer register will reset to point to the start of the transmit descriptor list.
RXEN	2	RW	Receive enable - when set, it enables the GEM to receive data. When reset frame reception will stop immediately and the receive pipeline will be cleared. The receive queue pointer register is unaffected.
LOOPEN	1	RW	Loop back local - asserts the loopback_local signal to the system clock generator. Also connects txd to rxd, tx_en to rx_dv and forces full duplex mode. Bit 11 of the network configuration register must be set low to disable TBI mode when in internal loopback. rx_clk and tx_clk may malfunction as the GEM is switched into and out of internal loop back. It is important that receive and transmit circuits have already been disabled when making the switch into and out of internal loop back.
LBEXT	0	RW	External loopback. Reset value: 0

15.5.1.2. NETWORK_CONFIG (0x0004)

Network configuration register.

The network configuration register contains functions for setting the mode of operation for the Gigabit Ethernet MAC

Symbol	Bit range	R/W	Description
unidir_en	31	RW	NA.
ignore_ipg_rx_er	30	RW	Ignore IPG rx_er. When set rx_er has no effect on the GEM's operation when rx_dv is low. Set this when using the RGMII wrapper in half-duplex mode.
BADPREAMBEN	29	RW	Receive bad preamble. When set frames with non-standard preamble are not rejected.
IPDSTRETCH	28	RW	IPG stretch enable - when set the transmit IPG can be increased above 96 bit times depending on the previous frame length using the IPG stretch register.
sgmii_en	27	RW	SGMII mode enable - changes behavior of the auto-negotiation advertisement and link partner ability registers to meet the requirements of SGMII and reduces the duration of the link timer from 10 ms to 1.6 ms
FCSIGNORE	26	RW	Ignore RX FCS - when set frames with FCS/CRC errors will not be rejected. FCS error statistics will still be collected for frames with bad FCS and FCS status will be recorded in frame's DMA descriptor. For normal operation this bit must be set to zero.
HDRXEN	25	RW	Enable frames to be received in half-duplex mode while transmitting.
RXCHKSUMEN	24	RW	Receive checksum offload enable - when set, the receive checksum engine is enabled. Frames with bad IP, TCP or UDP checksums are discarded.
PAUSECOPYDI	23	RW	Disable copy of pause frames - set to one to prevent valid pause frames being copied to memory. When set, pause frames are not copied to memory regardless of the state of the copy all frames bit; whether a hash match is found or whether a type ID match is identified. If a destination address match is found the pause frame will be copied to memory. Note that valid pause frames received will still increment pause statistics and pause the transmission of frames as required.
dbus_width	22-21	RW	Data bus width. Only valid bus widths may be written if the system is configured to a maximum width less than 128-bits. 00: 32 bit AMBA AHB data bus width 01: 64 bit AMBA AHB data bus width 10: 128 bit AMBA AHB data bus width 11: 128 bit AMBA AHB data bus width
MDCCLKDIV	20-18	RW	MDC clock division - set according to cpu_1xclk speed. These three bits determine the number cpu_1xclk will be divided by to generate MDC. For conformance with the 802.3 specification, MDC must not exceed 2.5 MHz (MDC is only active during MDIO read and write operations). 000: divide cpu_1xclk by 8 (cpu_1xclk up to 20 MHz) 001: divide cpu_1xclk by 16 (cpu_1xclk up to 40 MHz) 010: divide cpu_1xclk by 32 (cpu_1xclk up to 80 MHz) 011: divide cpu_1xclk by 48 (cpu_1xclk up to 120MHz) 100: divide cpu_1xclk by 64 (cpu_1xclk up to 160 MHz) 101: divide cpu_1xclk by 96 (cpu_1xclk up to 240 MHz) 110: divide cpu_1xclk by 128 (cpu_1xclk up to 320 MHz) 111: divide cpu_1xclk by 224 (cpu_1xclk up to 560 MHz)
FCSREM	17	RW	FCS remove - setting this bit will cause received frames to be written to memory without their frame check sequence (last 4 bytes). The frame length indicated will be reduced by four bytes in this mode.
LENGTHERRDSCRD	16	RW	Length field error frame discard - setting this bit causes frames with a measured length shorter than the extracted length field (as indicated by bytes 13 and 14 in a non-VLAN tagged frame) to be discarded. This only applies to frames with a length field less than 0x0600.
RXOFFS	15-14	RW	Receive buffer offset - indicates the number of bytes by which the received data is offset from the start of the receive buffer.
PAUSEEN	13	RW	Pause enable - when set, transmission will pause if a non zero 802.3 classic pause frame is received and PFC has not been negotiated.
RETRYTESTEN	12	RW	Retry test - must be set to zero for normal operation. If set to one the backoff between collisions will always be one slot time. Setting this bit to one helps test the too many retries condition. Also used in the pause frame tests to reduce the pause counter's decrement time from 512 bit times, to every rx_clk cycle.
pcs_sel	11	RW	N/A. 0: GMII/MII interface enabled, TBI disabled 1: TBI enabled, GMII/MII disabled
1000	10	RW	Gigabit mode enable - setting this bit configures the GEM for 1000 Mbps operation. 0: 10/100 operation using MII or TBI interface 1: Gigabit operation using GMII or TBI interface
EXTADDRMATCHEN	9	RW	External address match enable - when set the external address match interface can be used to copy frames to memory.
1536RXEN	8	RW	Receive 1536 byte frames - setting this bit means the GEM will accept frames up to 1536 bytes in length. Normally the GEM would reject any frame above 1518 bytes.
UCASTHASHEN	7	RW	Unicast hash enable - when set, unicast frames will be accepted when the 6 bit hash function of the destination address points to a bit that is set in the hash register.
MCASTHASHEN	6	RW	Multicast hash enable - when set, multicast frames will be accepted when the 6 bit hash function of the destination address points to a bit that is set in the hash register.
BCASTDI	5	RW	No broadcast - when set to logic one, frames addressed to the broadcast address of all ones will not be accepted.
COPYALLEN	4	RW	Copy all frames - when set to logic one, all valid frames will be accepted.
ENABLE_JUMBO_FRAME	3	RW	Enable Rx jumbo frames. Jumbo frame length up to 10240 bytes. Reset value: 0
NVLANDISC	2	RW	Discard non-VLAN frames - when set only VLAN tagged frames will be passed to the address matching logic.
FDEN	1	RW	Full duplex - if set to logic one, the transmit block ignores the state of collision and carrier sense and allows receive while transmitting. Also controls the half-duplex pin.
100	0	RW	Speed - set to logic one to indicate 100Mbps operation, logic zero for 10Mbps. The value of this pin is reflected on the speed_mode[0] output pin.

15.5.1.3. NETWORK_STATUS (0x0008)

Network status register

The network status register returns status information with respect to the PHY management interface.

Symbol	Bit range	R/W	Description
reserved	31-7	R	Reserved, read as zero.
pfc_pri_pause_neg	6	R	Set when PFC Priority Based Pause has been negotiated.
pcs_autoneg_pause_tx_res	5	R	N/A
pcs_autoneg_pause_rx_res	4	R	N/A
pcs_autoneg_dup_res	3	R	N/A
phy_mgmt_idle	2	R	The PHY management logic is idle (i.e. has completed).
MDIO	1	R	Returns status of the mdio_in pin
pcs_link_state	0	R	N/A

15.5.1.4. DMA_CONFIG (0x0010)

DMA configuration register

Symbol	Bit range	R/W	Description
reserved	31-25	R	Reserved, read as zero.
disc_when_no_ahb	24	RW	When set, the GEM DMA will automatically discard receive packets from the receiver packet buffer memory when no AHB resource is available. When low, then received packets will remain to be stored in the SRAM based packet buffer until AHB buffer resource next becomes available.
RXBUF	23-16	RW	DMA receive buffer size in AHB system memory. The value defined by these bits determines the size of buffer to use in main AHB system memory when writing received data. The value is defined in multiples of 64 bytes such that a value of 0x01 corresponds to buffers of 64 bytes, 0x02 corresponds to 128 bytes etc. For example: 0x02: 128 byte 0x18: 1536 byte (1max length frame/buffer) 0xA0: 10240 byte (110k jumbo frame/buffer) Note that this value should never be written as zero.
reserved	15-12	R	Reserved, read as zero.
TCPCKSUM	11	RW	Transmitter IP, TCP and UDP checksum generation offload enable. When set, the transmitter checksum generation engine is enabled, to calculate and substitute checksums for transmit frames. When clear, frame data is unaffected. If the GEM is not configured to use the DMA packet buffer, this bit is not implemented and will be treated as reserved, read as zero, ignored on write. Not implemented in PFE.
TXSIZE	10	RW	Transmitter packet buffer memory size select - Having this bit at zero halves the amount of memory used for the transmit packet buffer. This reduces the amount of memory used by the GEM. It is important to set this bit to one if the full configured physical memory is available. The value in brackets below represents the size that would result for the default maximum configured memory size of 4 kB. 1: Use full configured addressable space (4 kB) 0: Do not use top address bit (2 kB) If the GEM is not configured to use the DMA packet buffer, this bit is not implemented and will be treated as reserved, read as zero, ignored on write. Not implemented in PFE.
RXSIZE	9-8	RW	Receiver packet buffer memory size select - Having these bits at less than 11 reduces the amount of memory used for the receive packet buffer. This reduces the amount of memory used by the GEM. It is important to set these bits both to one if the full configured physical memory is available. The value in brackets below represents the size that would result for the default maximum configured memory size of 8 kBs. 00: Do not use top three address bits (1 kB) 01: Do not use top two address bits (2 kB) 10: Do not use top address bit (4 kB) 11: Use full configured addressable space (8 kB) If the controller is not configured to use the DMA packet buffer, these bits are not implemented and will be treated as reserved, read as zero, ignored on write. Not implemented in PFE.
ENDIAN	7	RW	AHB endian swap mode enable for packet data accesses - When set, selects swapped endianism for AHB transfers. When clear, selects little endian mode.
ahb_endian_swp_mgmt_en	6	RW	AHB endian swap mode enable for management descriptor accesses - When set, selects swapped endianism for AHB transfers. When clear, selects little endian mode.
reserved	5	R	Reserved, read as zero.
BLENGTH	4-0	RW	AHB fixed burst length for DMA data operations - Selects the burst length to attempt to use on the AHB when transferring frame data. Not used for DMA management operations and only used where space and data size allow. Otherwise SINGLE type AHB transfers are used. Upper bits become non-writeable if the configured DMA TX and RX FIFO sizes are smaller than required to support the selected burst size. One-hot priority encoding enforced automatically on register writes as follows, where 'x' represents don't care: 00001: Always use SINGLE AHB bursts 0001x: Always use SINGLE AHB bursts 001xx: Attempt to use INCR4 AHB bursts (default) 01xxx: Attempt to use INCR8 AHB bursts 1xxxx: Attempt to use INCR16 AHB bursts others: reserved

15.5.1.5. TXSR (0x0014)

Tx status register

This register, when read, provides details of the status of a transmit. Once read, individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register.

Symbol	Bit range	R/W	Description
reserved	31-9	R	Reserved, read as zero
HRESPNOK	8	RW	Hresp not OK - set when the DMA block sees hresp not OK. Cleared by writing a one to this bit.
late_collision	7	RW	Late collision occurred - only set if the condition occurs in gigabit mode, as retry is not attempted. Cleared by writing a one to this bit.
URUN	6	RW	Transmit under run - this bit is set if the transmitter was forced to terminate a frame that it had already began transmitting due to further data being unavailable. This bit is set if a transmitter status write back has not completed when another status write back is attempted. When using the DMA interface configured for internal FIFO mode, this bit is also set when the transmit DMA has written the SOP data into the FIFO and either the AHB bus was not granted in time for further data, or because an AHB not OK response was returned, or because a used bit was read. When using the DMA interface configured for packet buffer mode, this bit will never be set. When using the external FIFO interface, this bit is also set when the tx_r_underflow input is asserted during a frame transfer. Cleared by writing a 1.
TXCOMPL	5	RW	Transmit complete - set when a frame has been transmitted. Cleared by writing a one to this bit.
BUFEXH	4	RW	Transmit frame corruption due to AHB error - set if an error occurs whilst midway through reading transmit frame from the AHB, including HRESP errors and buffers exhausted mid frame (if the buffers run out during transmission of a frame then transmission stops, FCS shall be bad and tx_er asserted). Also set in DMA packet buffer mode if single frame is too large for configured packet buffer memory size. Cleared by writing a one to this bit.
TXGO	3	R	Transmit go - if high transmit is active. When using the exposed FIFO interface, this bit represents bit 3 of the network control register. When using the DMA interface this bit represents the tx_go variable as specified in the transmit buffer description.
RXOVR	2	RW	Retry limit exceeded - cleared by writing a one to this bit.
FRAMERX	1	RW	Collision occurred - set by the assertion of collision. Cleared by writing a one to this bit. When operating in 10/100 mode, this status indicates either a collision or a late collision. In gigabit mode, this status is not set for a late collision.
USEDREAD	0	RW	Used bit read - set when a transmit buffer descriptor is read with its used bit set. Cleared by writing a one to this bit.

15.5.1.6. RXQBASE (0x0018)

Rx queue base address. Not implemented in PFE

This register holds the start address of the receive buffer queue (receive buffers descriptor list). The receive buffer queue base address must be initialized before receive is enabled through bit 2 of the network control register. Once reception is enabled, any write to the receive buffer queue base address register is ignored. Reading this register returns the location of the descriptor currently being accessed. This value increments as buffers are used. Software should not use this register for determining where to remove received frames from the queue as it constantly changes as new frames are received. Software should instead work its way through the buffer descriptor queue checking the 'used' bits.

The descriptors should be aligned at 32-bit boundaries and the descriptors are written to using two individual non sequential accesses.

Symbol	Bit range	R/W	Description
rx_q_baseaddr	31-2	RW	Receive buffer queue base address - written with the address of the start of the receive queue.
reserved	1-0	R	Reserved, read as zero.

15.5.1.7. TXQBASE (0x001c)

Tx queue base address. Not implemented in PFE.

This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control register. Once transmission has started, any write to the transmit buffer queue base address register is illegal and therefore ignored.

Note that due to clock boundary synchronization, it takes a maximum of four pclk cycles from the writing of the transmit start bit before the transmitter is active. Writing to the transmit buffer queue base address register during this time may produce unpredictable results.

Reading this register returns the location of the descriptor currently being accessed. Since the DMA handles two frames at once, this may not necessarily be pointing to the current frame being transmitted.

The descriptors should be aligned at 32-bit boundaries and the descriptors are read from memory using two individual non sequential accesses.

Symbol	Bit range	R/W	Description
tx_q_baseaddr	31-2	RW	Transmit buffer queue base address - written with the address of the start of the transmit queue.
reserved	1-0	R	Reserved, read as zero.

15.5.1.8. RXSR (0x0020)

Rx status register

When read provides details of the status of a receive. Once read, individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register.

Symbol	Bit range	R/W	Description
reserved	31-4	R	Reserved, read as zero.
HRESPNOK	3	RW	Hresp not OK - set when the DMA block sees hresp not OK. Cleared by writing a one to this bit.
RXOVR	2	RW	Receive overrun - this bit is set if either the gem_dma RX FIFO or external RX FIFO were unable to store the receive frame due to a FIFO overflow, or if the receive status, reported by the gem_rx module to the gem_dma was not taken at end of frame. This bit is also set in DMA packet buffer mode if the packet buffer overflows. For DMA operation the buffer will be recovered if an overrun occurs. This bit is cleared by writing a one to it.
FRAMERX	1	RW	Frame received - one or more frames have been received and placed in memory. Cleared by writing a one to this bit.
BUFFNA	0	RW	Buffer not available - an attempt was made to get a new buffer and the pointer indicated that it was owned by the processor. The DMA will reread the pointer each time an end of frame is received until a valid pointer is found. This bit is set following each descriptor read attempt that fails, even if consecutive pointers are unsuccessful and software has in the mean time cleared the status flag. Cleared by writing a one to this bit.

15.5.1.9. ISR (0x0024)

Interrupt status register

Indicates an interrupt is asserted by the controller and is enabled (unmasked).

0: not asserted
1: asserted (if any bit reads as a 1, then the ethernet_int signal will be asserted to the interrupt controller)

Symbol	Bit range	R/W	Description
reserved	31-27	R	Reserved, read as zero.
tsu_sec_incr	26	RW	TSU second register increment interrupt. Write 1 to clear.
reserved	25-18	RW	Reserved
partner_pg_rx	17	RW	N/A
autoneg_complete	16	RW	N/A
ex_intr	15	RW	External interrupt - set when a rising edge has been detected on the ext_interrupt_in input pin. Write 1 to clear.
PAUSETX	14	RW	Pause frame transmitted- indicate a pause frame has been successfully transmitted after being initiated from the network control register or from the tx_pause control pin.
PAUSEZERO	13	RW	Pause time zero - et when either the pause time register at address 0x38 decrement to zero, or when a valid pause frame is received with a zero pause quantum field. Write 1 to clear.
PAUSENZERO	12	RW	Pause frame with non-zero pause quantum received- indicate a valid pause has been received that has a non-zero pause quantum field. Write 1 to clear.
HREPNOK	11	RW	Hresp not OK - et when the DMA block sees hresp not OK.
RXOVR	10	RW	Receive overrun - set when the receive overrun status bit get set.
link_chng	9	RW	N/A
reserved	8	R	Reserved
TXCOMPL	7	RW	Transmit complete - set when a frame has been transmitted.
TXEXH	6	R	Transmit frame corruption due to AHB error - set if an error occurs while midway through reading transmit frame from the AHB, including HRESP error and buffer exhausted mid frame (if the buffer run out during transmission of a frame then transmission top, FCS hall be bad and tx_er asserted). Also set in DMA packet buffer mode if single frame is too large for configured packet buffer memory size. Cleared on a read.
RETRY	5	RW	Retry limit exceeded or late collision- transmit error. Late collision will only cause this status bit to be set in gigabit mode (as a retry is not attempted).
reserved	4	RW	Reserved. Do not modify. Reset value: 0
TXUSED	3	RW	TX used bit read- set when a transmit buffer descriptor is read with it used bit set. Write 1 to clear.
RXUSED	2	RW	RX used bit read - set when a receive buffer descriptor is read with it used bit set. Write 1 to clear.
FRAMERX	1	RW	Receive complete- a frame has been stored in memory. Write 1 to clear.
MGMNT	0	RW	Management frame sent - the PHY maintenance register has completed its operation. Write 1 to clear.

15.5.1.10. IER (0x0028)

Interrupt enable register

Enable interrupts by writing a 1 to one or more bits.

Write a 1 to enable (unmask) the interrupt.

Writing 0 has no affect on the mask bit.

When read, this register returns zero. To control interrupt masks and read status, use the interrupt status, enable, disable and mask registers together. At reset, all interrupts are disabled (masked).

Refer to the table for ISR.

15.5.1.11. IDR (0x002c)

Interrupt disable register

Disable interrupts by applying a mask to one or more bits.

Write 1 to disable (mask) the interrupt.

Writing 0 has no affect on the mask bit.

When read, this register returns zero.

Refer to the table for ISR.

15.5.1.12. IMR (0x0030)

Interrupt mask status register

Indicates the mask state of each interrupt.

0: interrupt non masked (enabled)

1: interrupt masked (disabled), reset default

All interrupts are disabled after a module reset. The interrupt masks are individually controlled using the write-only interrupt enable and disable registers.

For test purposes there is a write-only function to the interrupt mask register that allows the bits in the interrupt status register to be set or cleared, regardless of the state of the mask register.

15.5.1.13. PHY_MANAGEMENT (0x0034)

PHY management register

The PHY maintenance register is implemented as a shift register. Writing to the register starts a shift operation, which is signaled as complete when bit-2 is set in the network status register. It takes about 2000 pclk cycles to complete, when MDC is set for pclk divide by 32 in the network configuration register. An interrupt is generated upon completion. During this time, the MSB of the register is output on the MDIO pin and the LSB updated from the MDIO pin with each MDC cycle. This causes transmission of a PHY management frame on MDIO. See Section 22.2.4.5 of the IEEE 802.3 standard. Reading during the shift operation will return the current contents of the shift register. At the end of management operation, the bits will have shifted back to their original locations. For a read operation, the data bits will be updated with data read from the PHY. It is important to write the correct values to the register to ensure a valid PHY management frame is produced.

Symbol	Bit range	R/W	Description
reserved	31	RW	Must be zero.
clause_22	30	RW	Must be written to 1 for Clause 22 operation. Check your PHY's spec to see if it is clause 22 or clause 45 compliant.
OP	29-28	RW	Operation. 10 is read. 01 is write.
ADDR	27-23	RW	PHY address
REG	22-18	RW	Register address - specifies the register in the PHY to access.
must_10	17-16	RW	Turnaround time. Must be written to 10.
DATA	15-0	RW	For a write operation this is written with the data to be written to the PHY. After a read operation this contains the data read from the PHY.

15.5.1.14. RXPAUSE (0x0038)

Received pause quantum

Symbol	Bit range	R/W	Description
reserved	31-16	R	Reserved, read as zero.
rx_pauseq	15-0	R	Received pause quantum - stores the current value of the received pause quantum register which is decremented every 512 bit times.

15.5.1.15. TXPAUSE (0x003c)

Transmit pause quantum

Symbol	Bit range	R/W	Description
reserved	31-16	R	Reserved, read as zero.
tx_pauseq	15-0	RW	Transmit pause quantum - written with the pause quantum value for pause frame transmission.

15.5.1.16. HASH_BOT (0x0080)

Hash register bottom

The unicast hash enable and the multicast hash enable bits in the network configuration register enable the reception of hash matched frames.

Symbol	Bit range	R/W	Description
HASHL	31-0	RW	The first 32 bits of the hash address register.

15.5.1.17. HASH_TOP (0x0084)

Hash register top

The unicast hash enable and the multicast hash enable bits in the network configuration register enable the reception of hash matched frames.

Symbol	Bit range	R/W	Description
HASHH	31-0	RW	The remaining 32 bits of the hash address register.

15.5.1.18. SPEC1_ADD_BOT (0x0088)

Specific address 1 bottom

Symbol	Bit range	R/W	Description
LADDR1L	31-0	RW	Least significant 32 bits of the destination address, that is bits 31:0. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received. MAC address bytes in order: 0 1 2 3

15.5.1.19. SPEC1_ADD_TOP (0x008c)

Specific address 1 top

Symbol	Bit range	R/W	Description
reserved	31-16	R	Reserved, read as zero
LADDR1H	15-0	RW	Specific address 1. The most significant bits of the destination address, that is bits 47:32. MAC address bytes in order: x x 4 5

15.5.1.20. SPEC2_ADD_BOT (0x0090)

Specific address 2 bottom

Symbol	Bit range	R/W	Description
LADDR2L	31-0	RW	Least significant 32 bits of the destination address, that is bits 31:0. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received.

15.5.1.21. SPEC2_ADD_TOP (0x0094)

Specific address 2 top

Symbol	Bit range	R/W	Description
reserved	31-16	R	Reserved, read as zero
LADDR2H	15-0	RW	Specific address 2. The most significant bits of the destination address, that is bits 47:32.

15.5.1.22. SPEC3_ADD_BOT (0x0098)

Specific address 3 bottom

Symbol	Bit range	R/W	Description
LADDR3L	31-0	RW	Least significant 32 bits of the destination address, that is bits 31:0. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received.

15.5.1.23. SPEC3_ADD_TOP (0x009c)

Specific address 1 top

Symbol	Bit range	R/W	Description
reserved	31-16	R	Reserved, read as zero
LADDR3H	15-0	RW	Specific address 3. The most significant bits of the destination address, that is bits 47:32.

15.5.1.24. SPEC4_ADD_BOT (0x00a0)

Specific address 4 bottom

Symbol	Bit range	R/W	Description
LADDR4L	31-0	RW	Least significant 32 bits of the destination address, that is bits 31:0. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received.

15.5.1.25. MATCH1 (0x00a8)

Type ID match 1

Symbol	Bit range	R/W	Description
copy_en	31	RW	Enable copying of type ID match 1 matched frames
reserved	30-16	R	Reserved, read as zero
type_id_match1	15-0	RW	Type ID match 1. For use in comparisons with received frames type ID/length field.

15.5.1.26. MATCH2 (0x00ac)

Type ID match 2

Symbol	Bit range	R/W	Description
copy_en	31	RW	Enable copying of type ID match 2 matched frames
reserved	30-16	R	Reserved, read as zero
type_id_match2	15-0	RW	Type ID match 2. For use in comparisons with received frames type ID/length field.

15.5.1.27. MATCH3 (0x00b0)

Type ID match 3

Symbol	Bit range	R/W	Description
copy_en	31	RW	Enable copying of type ID match 3 matched frames
reserved	30-16	R	Reserved, read as zero
type_id_match3	15-0	RW	Type ID match 3. For use in comparisons with received frames type ID/length field.

15.5.1.28. MATCH4 (0x00b4)

Type ID match 4

Symbol	Bit range	R/W	Description
copy_en	31	RW	Enable copying of type ID match 4 matched frames
reserved	30-16	R	Reserved, read as zero
type_id_match4	15-0	RW	Type ID match 4. For use in comparisons with received frames type ID/length field.

15.5.1.29. WOL_ENABLE (0x00b8)

Wake on LAN Register

Symbol	Bit range	R/W	Description
reserved	31-20	R	Reserved, read as zero
multi_hash_en	19	RW	Wake on LAN multicast hash event enable. When set multicast hash events will cause the wol output to be asserted.
spec_addr_reg1_en	18	RW	Wake on LAN specific address register 1 event enable. When set specific address 1 events will cause the wol output to be asserted.
arp_req_en	17	RW	Wake on LAN ARP request event enable. When set ARP request events will cause the wol output to be asserted.
magic_pkt_en	16	RW	Wake on LAN magic packet event enable. When set magic packet events will cause the wol output to be asserted.
arp_req_ip_addr	15-0	RW	Wake on LAN ARP request IP address. Written to define the least significant 16 bits of the target IP address that is matched to generate a Wake on LAN event. A value of zero will not generate an event, even if this is matched by the received frame.

15.5.1.30. STRETCH (0x00bc)

IPG stretch register

Symbol	Bit range	R/W	Description
reserved	31-16	R	Reserved, read as zero
ipg_stretch	15-0	RW	Bits 7:0 are multiplied with the previously transmitted frame length (including preamble) bits 15:8 +1 divide the frame length. If the resulting number is greater than 96 and bit 28 is set in the network configuration register then the resulting number is used for the transmit inter-packet-gap. 1 is added to bits 15:8 to prevent a divide by zero.

15.5.1.31. STACKED_VLAN (0x00c0)

Stacked VLAN register

Symbol	Bit range	R/W	Description
stacked_vlan_en	31	RW	Enable Stacked VLAN processing mode
reserved	30-16	R	Reserved, read as zero
user_def_vlan_type	15-0	RW	User defined VLAN_TYPE field. When Stacked VLAN is enabled, the first VLAN tag in a received frame will only be accepted if the VLAN type field is equal to this user defined VLAN_TYPE OR equal to the standard VLAN type (0x8100). Note that the second VLAN tag of a Stacked VLAN packet will only be matched correctly if its VLAN_TYPE field equals 0x8100.

15.5.1.32. TX_PFC_PAUSE (0x00c4)

Transmit PFC pause register

Symbol	Bit range	R/W	Description
reserved	31-16	R	Reserved, read as zero
pauseq_sel	15-8	RW	If bit 17 of the network control register is written with a one then for each entry equal to zero in the Transmit PFC Pause Register[15:8], the PFC pause frame's pause quantum field associated with that entry will be taken from the transmit pause quantum register. For each entry equal to one in the Transmit PFC Pause Register [15:8], the pause quantum associated with that entry will be zero.
pri_en_vec_val	7-0	RW	If bit 17 of the network control register is written with a one then the priority enable vector of the PFC priority based pause frame will be set equal to the value stored in this register [7:0].

15.5.1.33. SPEC1_ADD_MASK_BOT (0x00c8)

Specific address 1 mask bottom

Symbol	Bit range	R/W	Description
mask_bits_bot	31-0	RW	Setting a bit to one masks the corresponding bit in the specific address 1 register

15.5.1.34. SPEC1_ADD_MASK_TOP (0x00cc)

Specific address 1 mask top

Symbol	Bit range	R/W	Description
reserved	31-16	R	Reserved, read as zero
mask_bits_top	15-0	RW	Setting a bit to one masks the corresponding bit in the specific address 1 register

15.5.1.35. EFTSH (0x00e8)

PTP Event Frame Transmitted Seconds Register

15.5.1.36. EFRSH (0x00ec)

PTP Event Frame Received Seconds Register

15.5.1.37. PEFTSH (0x00f0)

PTP Peer Event Frame Transmitted Seconds Register

15.5.1.38. PEFRSH (0x00f4)

PTP Peer Event Frame Received Seconds Register

15.5.1.39. MODULE_ID (0x00fc)

Module ID

This register indicates a Cadence module identification number and module revision. The value of this register is read only as defined by `gem_revision_reg_value. With GEM p23, it is 0x00020118. The GEM in the PFE is 0x0002011d.

Symbol	Bit range	R/W	Description
module_id	31-16	R	Module identification number - for the GEM, this value is fixed at 0x0002.
module_rev	15-0	R	Module revision - fixed byte value specific to the revision of the design which is incremented after each release of the IP.

15.5.1.40. OCTETS_TX_BOT (0x0100)

Octets transmitted 31:0] (in frames without error)

Bits 31:0 should be read prior to bits 47:32 to ensure reliable operation. In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.

For test purposes, it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes.

Once a statistics register has been read, it is automatically cleared.

Symbol	Bit range	R/W	Description
octets_tx_bot	31-0	R	Transmitted octets in frame without errors [31:0]. The number of octets transmitted in valid frames of any type. This counter is 48-bits, and is read through two registers. This count does not include octets from automatically generated pause frames.

15.5.1.41. OCTETS_TX_TOP (0x0104)

Octets transmitted [47:32] (in frames without error)

Once a statistics register has been read, it is automatically cleared.

Symbol	Bit range	R/W	Description
reserved	31-16	R	Reserved, read as zero.
octets_tx_top	15-0	R	Transmitted octets in frame without errors [47:32]. The number of octets transmitted in valid frames of any type. This counter is 48-bits, and is read through two registers. This count does not include octets from automatically generated pause frames.

15.5.1.42. FRAMES_TX (0x0108)

Frames transmitted

Statistical counter for Frames transmitted without an error and exclude pause frames.

NOTES for ALL Statistical registers for Frames Transferred:

The a statistical counter is read by software, it is cleared to zero by the hardware. When a counter reaches its maximum value, it stops counting and is read with all 1s. The statistical counters must be read frequently enough if data loss is to be prevented.

For test purposes, all of the statistical counters may be written to (not just read) by setting bit 7 (wren_stat_regs) in the network control register. Also for test purposes, all of the statistical counters can be incremented (by one) by writing a 1 to bit 6 (incr_stat_regs) of the network control register.

Symbol	Bit range	R/W	Description
FRAMES_TX	31-0	R	Frames transmitted without error. A 32 bit register counting the number of frames successfully transmitted, i.e., no under run and not too many retries. Excludes pause frames.

15.5.1.43. BROADCAST_TX (0x010c)

Broadcast frames Tx

Statistical counter for Broadcast Frames transmitted without an error and exclude pause frames. Refer to the FRAMES_TX register for additional information.

Symbol	Bit range	R/W	Description
BROADCAST_TX	31-0	R	Broadcast frames transmitted without error. A 32 bit register counting the number of broadcast frames successfully transmitted without error, i.e., no under run and not too many retries. Excludes pause frames.

15.5.1.44. MULTICAST_TX (0x0110)

Multicast frames Tx

Statistical counter for Multicast Frames transmitted without an error and exclude pause frames. Refer to the FRAMES_TX register for additional information.

Symbol	Bit range	R/W	Description
MULTICAST_TX	31-0	R	Multicast frames transmitted without error. A 32 bit register counting the number of multicast frames successfully transmitted without error, i.e., no under run and not too many retries. Excludes pause frames.

15.5.1.45. PAUSE_TX (0x0114)

Pause frames Tx

Statistical counter for Pause Frames transmitted without an error and not sent through the FIFO interface. Refer to the FRAMES_TX register for additional information.

Symbol	Bit range	R/W	Description
reserved	31-16	R	Reserved, read as zero.
pause_frames_tx	15-0	R	Transmitted pause frames - a 16 bit register counting the number of pause frames transmitted. Only pause frames triggered by the register interface or through the external pause pins are counted as pause frames. Pause frames received through the external FIFO interface are counted in the frames transmitted counter.

15.5.1.46. FRAME64_TX (0x0118)

Frames Tx, 64-byte length

Statistical counter of frames of 64 bytes that are transmitted without error. Does not include pause frames. Refer to the FRAMES_TX register for additional information.

Symbol	Bit range	R/W	Description
FRAME64_TX	31-0	R	64 byte frames transmitted without error. A 32 bit register counting the number of 64 byte frames successfully transmitted without error, i.e., no under run and not too many retries. Excludes pause frames.

15.5.1.47. FRAME65_127_TX (0x011c)

Frames Tx, 65 to 127-byte length

Statistical counter of frames of 65 to 127 bytes that are transmitted without error. Does not include pause frames. Refer to the FRAMES_TX register for additional information.

Symbol	Bit range	R/W	Description
FRAME65_127_TX	31-0	R	65 to127 byte frames transmitted without error. A 32 bit register counting the number of 65 to 127 byte frames successfully transmitted without error, i.e., no under run and not too many retries.

15.5.1.48. FRAME128_255_TX (0x0120)

Frames Tx, 128 to 255-byte length

Statistical counter of frames of 128 to 255 bytes that are transmitted without error. Does not include pause frames. Refer to the FRAMES_TX register for additional information.

Symbol	Bit range	R/W	Description
FRAME128_255_TX	31-0	R	128 to 255 byte frames transmitted without error. A 32 bit register counting the number of 128 to 255 byte frames successfully transmitted without error, i.e., no under run and not too many retries.

15.5.1.49. FRAME256_511_TX (0x0124)

Frames Tx, 256 to 511-byte length

Statistical counter of frames of 256 to 511 bytes that are transmitted without error. Does not include pause frames. Refer to the FRAMES_TX register for additional information.

Symbol	Bit range	R/W	Description
FRAME256_511_TX	31-0	R	256 to 511 byte frames transmitted without error. A 32 bit register counting the number of 256 to 511 byte frames successfully transmitted without error, i.e., no under run and not too many retries.

15.5.1.50. FRAME512_1023_TX (0x0128)

Frames Tx, 512 to 1023-byte length

Statistical counter of frames of 512 to 1023 bytes that are transmitted without error. Does not include pause frames. Refer to the FRAMES_TX register for additional information.

Symbol	Bit range	R/W	Description
FRAME512_1023_TX	31-0	R	512 to 1023 byte frames transmitted without error. A 32 bit register counting the number of 512 to 1023 byte frames successfully transmitted without error, i.e., no under run and not too many retries.

15.5.1.51. FRAME1024_1518_TX (0x012c)

Frame Tx, 1024 to 1518-byte length

Statistical counter of frames of 1024 to 1518 bytes that are transmitted without error. Does not include pause frames. Refer to the FRAMES_TX register for additional information.

Symbol	Bit range	R/W	Description
FRAME1024_1518_TX	31-0	R	1024 to 1518 byte frames transmitted without error. A 32 bit register counting the number of 1024 to 1518 byte frames successfully transmitted without error, i.e., no under run and not too many retries.

15.5.1.52. FRAME1519_TX (0x0130)

Frame Tx, 1519-byte length or more

Statistical counter of frames of 1519 bytes or more that are transmitted without error. Does not include pause frames. Refer to the FRAMES_TX register for additional information.

Symbol	Bit range	R/W	Description
FRAME1519_TX	31-0	R	1519 bytes or more frames transmitted without error. A 32 bit register counting the number of 1519 byte or more frames successfully transmitted without error, i.e., no under run and not too many retries.

15.5.1.53. TX_URUN (0x0134)

Transmit under runs

In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.

Once a statistics register has been read, it is automatically cleared.

Symbol	Bit range	R/W	Description
reserved	31-10	R	Reserved, read as zero.
tx_under_runs	9-0	R	Transmit under runs - a 10 bit register counting the number of frames not transmitted due to a transmit under run. If this register is incremented then no other statistics register is incremented.

15.5.1.54. SINGLE_COL (0x0138)

Single collision frames

In statistics register block. Is reset to zero on a read and sticks at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.

Once a statistics register has been read, it is automatically cleared.

Symbol	Bit range	R/W	Description
reserved	31-18	R	Reserved, read as zero.
single_collisn	17-0	R	Single collision frames - an 18 bit register counting the number of frames experiencing a single collision before being successfully transmitted, i.e. no under run.

15.5.1.55. MULTI_COL (0x013c)

Multiple collision frames

In statistics register block. Is reset to zero on a read and sticks at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.

Once a statistics register has been read, it is automatically cleared.

Symbol	Bit range	R/W	Description
reserved	31-18	R	Reserved, read as zero.
multi_collisn	17-0	R	Multiple collision frames - an 18 bit register counting the number of frames experiencing between two and fifteen collisions prior to being successfully transmitted, i.e., no under run and not too many retries.

15.5.1.56. EXCESS_COL (0x0140)

Excessive collisions

In statistics register block. Is reset to zero on a read and sticks at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.

Once a statistics register has been read, it is automatically cleared.

Symbol	Bit range	R/W	Description
reserved	31-10	R	Reserved, read as zero.
excessive_collisns	9-0	R	Excessive collisions - a 10 bit register counting the number of frames that failed to be transmitted because they experienced 16 collisions.

15.5.1.57. LATE_COL (0x0144)

Late collisions

In statistics register block. Is reset to zero on a read and sticks at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.

Once a statistics register has been read, it is automatically cleared.

Symbol	Bit range	R/W	Description
reserved	31-10	R	Reserved, read as zero.
late_collisns	9-0	R	Late collisions - a 10 bit register counting the number of late collision occurring after the slot time (512 bits) has expired. In 10/100 mode, late collisions are counted twice i.e., both as a collision and a late collision. In gigabit mode, a late collision causes the transmission to be aborted, thus the single and multi collision registers are not updated.

15.5.1.58. DEF_TX (0x0148)

Deferred transmission frames

In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.

Once a statistics register has been read, it is automatically cleared.

Symbol	Bit range	R/W	Description
reserved	31-18	R	Reserved, read as zero.
deferred_tx	17-0	R	Deferred transmission frames - an 18 bit register counting the number of frames experiencing deferral due to carrier sense being active on their first attempt at transmission. Frames involved in any collision are not counted nor are frames that experienced a transmit under run.

15.5.1.59. CRS_ERRORS (0x014c)

Carrier sense errors

In statistics register block. Is reset to zero on a read and sticks at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.

Once a statistics register has been read, it is automatically cleared.

Symbol	Bit range	R/W	Description
reserved	31-10	R	Reserved, read as zero.
carrier_sense_errs	9-0	R	Carrier sense errors - a 10 bit register counting the number of frames transmitted where carrier sense was not seen during transmission or where carrier sense was deasserted after being asserted in a transmit frame without collision (no under run). Only incremented in half duplex mode. The only effect of a carrier sense error is to increment this register. The behavior of the other statistics registers is unaffected by the detection of a carrier sense error.

15.5.1.60. OCTETS_RX_BOT (0x0150)

Octets received [31:0]

Bits 31:0 should be read prior to bits 47:32 to ensure reliable operation. In statistics register block. Is reset to zero on a read and sticks at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.

Once a statistics register has been read, it is automatically cleared.

Symbol	Bit range	R/W	Description
octets_rx_bot	31-0	R	Received octets in frame without errors [31:0]. The number of octets received in valid frames of any type. This counter is 48-bits and is read through two registers. This count does not include octets from pause frames, and is only incremented if the frame is successfully filtered and copied to memory.

15.5.1.61. OCTETS_RX_TOP (0x0154)

Octets receives [47:32]

Once a statistics register has been read, it is automatically cleared.

Symbol	Bit range	R/W	Description
reserved	31-10	R	Reserved, read as zero.
octets_rx_top	9-0	R	Received octets in frame without errors [47:32]. The number of octets received in valid frames of any type. This counter is 48-bits and is read through two registers. This count does not include octets from pause frames, and is only incremented if the frame is successfully filtered and copied to memory.

15.5.1.62. FRAMES_RX (0x0158)

Frames received

Statistical counter for Frames received without an error and exclude pause frames.

NOTES for ALL Statistical registers for Frames Transferred:

Symbol	Bit range	R/W	Description
FRAMES_RX	31-0	R	Frames received without error. A 32 bit register counting the number of frames successfully received. Excludes pause frames, and is only incremented if the frame is successfully filtered and copied to memory.

15.5.1.63. BROADCAST_RX (0x015c)

Broadcast frames Rx

Statistical counter for Broadcast Frames received without an error and exclude pause frames. Refer to the FRAMES_RX register for additional information.

Symbol	Bit range	R/W	Description
BROADCAST_RX	31-0	R	Broadcast frames received without error. A 32 bit register counting the number of broadcast frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered and copied to memory.

15.5.1.64. MULTICAST_RX (0x0160)

Multicast frames Rx

Statistical counter for Multicast Frames received without an error and exclude pause frames. Refer to the FRAMES_RX register for additional information.

Symbol	Bit range	R/W	Description
MULTICAST_RX	31-0	R	Multicast frames received without error. A 32 bit register counting the number of multicast frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered and copied to memory.

15.5.1.65. PAUSE_RX (0x0164)

Pause frames Rx

Statistical counter for Pause Frames received without an error. Refer to the FRAMES_RX register for additional information.

Symbol	Bit range	R/W	Description
reserved	31-16	R	Reserved, read as zero
pause_rx	15-0	R	Received pause frames - a 16 bit register counting the number of pause frames received without error.

15.5.1.66. FRAME64_RX (0x0168)

Frames Rx, 64-byte length

Statistical counter for frames of 64 bytes in length that are received without an error and exclude pause frames. Refer to the FRAMES_RX register for additional information.

Symbol	Bit range	R/W	Description
FRAME64_RX	31-0	R	64 byte frames received without error. A 32 bit register counting the number of 64 byte frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered and copied to memory.

15.5.1.67. FRAME65_127_RX (0x016c)

Frames Rx, 65 to 127-byte length

Statistical counter for frames of 65 to 127 bytes in length that are received without an error and exclude pause frames. Refer to the FRAMES_RX register for additional information.

Symbol	Bit range	R/W	Description
FRAME65_127_RX	31-0	R	65 to 127 byte frames received without error. A 32 bit register counting the number of 65 to 127 byte frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered and copied to memory.

15.5.1.68. FRAME128_255_RX (0x0170)

Frames Rx, 128 to 255-byte length

Statistical counter for frames of 128 to 255 bytes in length that are received without an error and exclude pause frames. Refer to the FRAMES_RX register for additional information.

Symbol	Bit range	R/W	Description
FRAME128_255_RX	31-0	R	128 to 255 byte frames received without error. A 32 bit register counting the number of 128 to 255 byte frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered and copied to memory.

15.5.1.69. FRAME256_511_RX (0x0174)

Frames Rx, 256 to 511-byte length

Statistical counter for frames of 256 to 511 bytes in length that are received without an error and exclude pause frames. Refer to the FRAMES_RX register for additional information.

Symbol	Bit range	R/W	Description
FRAME256_511_RX	31-0	R	256 to 511 byte frames received without error. A 32 bit register counting the number of 256 to 511 byte frames successfully transmitted without error. Excludes pause frames, and is only incremented if the frame is successfully filtered and copied to memory.

15.5.1.70. FRAME512_1023_RX (0x0178)

Frames Rx, 512 to 1023-byte length

Statistical counter for frames of 512 to 1023 bytes in length that are received without an error and exclude pause frames. Refer to the FRAMES_RX register for additional information.

Symbol	Bit range	R/W	Description
FRAME512_1023_RX	31-0	R	512 to 1023 byte frames received without error. A 32 bit register counting the number of 512 to 1023 byte frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered and copied to memory.

15.5.1.71. FRAME1024_1518_RX (0x017c)

Frames Rx, 1024 to 1518-byte length

Statistical counter for frames of 1024 to 1518 bytes in length that are received without an error and exclude pause frames. Refer to the FRAMES_RX register for additional information.

Symbol	Bit range	R/W	Description
FRAME1024_1518_RX	31-0	R	1024 to 1518 byte frames received without error. A 32 bit register counting the number of 1024 to 1518 byte frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered and copied to memory.

15.5.1.72. FRAME1519_RX (0x0180)

Frames Rx, 1519 byte length or more

Statistical counter for frames of 1519 bytes or more in length that are received without an error and exclude pause frames. Refer to the FRAMES_RX register for additional information.

Symbol	Bit range	R/W	Description
FRAME1519_RX	31-0	R	1519 bytes or more frames received without error. A 32 bit register counting the number of 1519 bytes or more frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered and copied to memory.

15.5.1.73. USIZE_FRAMES (0x0184)

Undersize frames received

Symbol	Bit range	R/W	Description
reserved	31-10	R	Reserved, read as zero.
undersz_rx	9-0	R	Undersize frames received - a 10 bit register counting the number of frames received less than 64 bytes in length (10/100 mode or gigabit mode, full duplex) that do not have either a CRC error or an alignment error.

15.5.1.74. EXCESS_LENGTH (0x0188)

Oversize frames received

Symbol	Bit range	R/W	Description
reserved	31-10	R	Reserved, read as zero.
oversz_rx	9-0	R	Oversize frames received - a 10 bit register counting the number of frames received exceeding 1518 bytes (1536 bytes if bit 8 is set in network configuration register) in length but do not have either a CRC error, an alignment error nor a receive symbol error.

15.5.1.75. JABBERS (0x018c)

Jabbers received

Symbol	Bit range	R/W	Description
reserved	31-10	R	Reserved, read as zero.
jab_rx	9-0	R	Jabbers received - a 10 bit register counting the number of frames received exceeding 1518 bytes (1536 if bit 8 set in network configuration register) in length and have either a CRC error, an alignment error or a receive symbol error.

15.5.1.76. FCS_ERRORS (0x0190)

Frame check sequence errors

Symbol	Bit range	R/W	Description
reserved	31-10	R	Reserved, read as zero.
fcs_errors	9-0	R	Frame check sequence errors - a 10 bit register counting frames that are an integral number of bytes, have bad CRC and are between 64 and 1518 bytes in length. This register is also incremented if a symbol error is detected and the frame is of valid length and has an integral number of bytes. This register is incremented for a frame with bad FCS, regardless of whether it is copied to memory due to ignore FCS mode being enabled in bit 26 of the network configuration register.

15.5.1.77. LENGTH_CHECK_ERRORS (0x0194)

Length field frame errors

Symbol	Bit range	R/W	Description
reserved	31-10	R	Reserved, read as zero.
length_field_errors	9-0	R	Length field frame errors - this 10-bit register counts the number of frames received that have a measured length shorter than that extracted from the length field (bytes 13 and 14). This condition is only counted if the value of the length field is less than 0x0600, the frame is not of excessive length and checking is enabled through bit 16 of the network configuration register.

15.5.1.78. RX_SYMBOL_ERRORS (0x0198)

Receive symbol errors

Symbol	Bit range	R/W	Description
reserved	31-10	R	Reserved, read as zero.
rx_symbol_errors	9-0	R	Receive symbol errors - a 10-bit register counting the number of frames that had rx_er asserted during reception. For 10/100 mode symbol errors are counted regardless of frame length checks. For gigabit mode the frame must satisfy slot time requirements in order to count a symbol error.

15.5.1.79. ALIGN_ERRORS (0x019c)

Alignment errors

Symbol	Bit range	R/W	Description
reserved	31-10	R	Reserved, read as zero.
align_errors	9-0	R	Alignment errors - a 10 bit register counting frames that are not an integral number of bytes long and have bad CRC when their length is truncated to an integral number of bytes and are between 64 and 1518 bytes in length. This register is also incremented if a symbol error is detected and the frame is of valid length and does not have an integral number of bytes.

15.5.1.80. RX_RES_ERRORS (0x01a0)

Receive resource errors

Symbol	Bit range	R/W	Description
reserved	31-18	R	Reserved, read as zero.
rx_resource_errors	17-0	R	Receive resource errors - an 18 bit register counting the number of frames that were successfully received by the MAC (correct address matched frame and adequate slot time) but could not be copied to memory because no receive buffer was available. This will be either because the AHB bus was not granted in time or because a hresp not OK was returned.

15.5.1.81. RX_ORUN (0x01a4)

Receive overrun errors

Symbol	Bit range	R/W	Description
reserved	31-10	R	Reserved, read as zero.
rx_overrun_errors	9-0	R	Receive overruns - a 10 bit register counting the number of frames that are address recognized but were not copied to memory due to a receive overrun.

15.5.1.82. IP_CKSUM (0x01a8)

IP header checksum errors

Symbol	Bit range	R/W	Description
reserved	31-8	R	Reserved, read as zero.
ip_hdr_csum_errors	7-0	R	IP header checksum errors - an 8-bit register counting the number of frames discarded due to an incorrect IP header checksum, but are between 64 and 1518 bytes and do not have a CRC error, an alignment error, nor a symbol error.

15.5.1.83. TCP_CKSUM (0x01ac)

TCP checksum errors

Symbol	Bit range	R/W	Description
reserved	31-8	R	Reserved, read as zero.
tcp_csum_errors	7-0	R	TCP checksum errors - an 8-bit register counting the number of frames discarded due to an incorrect TCP checksum, but are between 64 and 1518 bytes and do not have a CRC error, an alignment error, nor a symbol error.

15.5.1.84. UDP_CKSUM (0x01b0)

UDP checksum error

Symbol	Bit range	R/W	Description
reserved	31-8	R	Reserved, read as zero.
udp_csum_errors	7-0	R	UDP checksum errors - an 8-bit register counting the number of frames discarded due to an incorrect UDP checksum, but are between 64 and 1518 bytes and do not have a CRC error, an alignment error, nor a symbol error.

15.5.1.85. TISUBN (0x01bc)

1588 Timer Increment Sub-ns

Must be written before writing to TI.

Symbol	Bit range	R/W	Description
SUBNSINCRL	31-24	RW	Subns[7:0]
SUBNSINCRH	15-0	RW	Subns[23:8]

15.5.1.86. TSH (0x01c0)

1588 Timer Seconds High

Symbol	Bit range	R/W	Description
reserved	31-16	R	Reserved, read as zero.
TSH	15-0	R	TSU timer value (s). MSB [47:32] of seconds timer count

15.5.1.87. TSL (0x01d0)

1588 Timer Seconds Low

Symbol	Bit range	R/W	Description
TSL	31-0	R	TSU timer value (s). LSB [31:0] of seconds timer count

15.5.1.88. TN (0x01d4)

1588 Timer Nanoseconds

Symbol	Bit range	R/W	Description
reserved	31-30	R	Reserved, read as zero.
TN	29-0	R	TSU timer value (ns)

15.5.1.89. TA (0x01d8)

1588 Timer Adjust

Symbol	Bit range	R/W	Description
ADDSUB	31	W	Timer adjust operation. 0=add 1=subtract
reserved	30	R	Reserved, read as zero.
NSADJ	29-0	W	Nanoseconds to add/subtract to timer

15.5.1.90. TI (0x01dc)

1588 Timer Increment

The TI register must be written after the TISUBN register and the write operation will cause the values written to both registers to take effect.

Symbol	Bit range	R/W	Description
reserved	31-8	R	Reserved, read as zero.
NSINCR	7-0	R	Nanoseconds timer increment

15.5.1.91. EFTSL (0x01e0)

PTP Event Frame Tx Seconds Low

15.5.1.92. EFTN (0x01e4)

PTP Event Frame Tx Nanoseconds

15.5.1.93. EFRSL (0x01e8)

PTP Event Frame Rx Seconds Low

15.5.1.94. EFRN (0x01ec)

PTP Event Frame Rx Nanoseconds

15.5.1.95. PEFTSL (0x01f0)

PTP Peer Event Frame Tx Secs Low

15.5.1.96. PEFTN (0x01f4)

PTP Peer Event Frame Tx Ns

15.5.1.97. PEFRSL (0x01f8)

PTP Peer Event Frame Rx Sec Low

15.5.1.98. PEFRN (0x01fc)

PTP Peer Event Frame Rx Ns

15.5.1.99. PCSCNTRL (0x0200)

PCS Control

Symbol	Bit range	R/W	Description
PCSAUTONEG	12	RW	?

15.5.1.100. PCSSTS (0x0204)

PCS Status

15.5.1.101. PCSPHYTOPID (0x0208)

PCS PHY Top ID

15.5.1.102. PCSPHYBOTID (0x020c)

PCS PHY Bottom ID

15.5.1.103. PCSANADV (0x0210)

PCS AN Advertisement

15.5.1.104. PCSANLPBASE (0x0214)

PCS AN Link Partner Base

15.5.1.105. PCSANEXP (0x0218)

PCS AN Expansion

15.5.1.106. PCSANNPTX (0x021c)

PCS AN Next Page TX

15.5.1.107. PCSANNPLP (0x0220)

PCS AN Next Page LP

15.5.1.108. PCSANEXTSTS (0x023c)

PCS AN Extended Status

15.5.1.109. DESIGN_CFG1 (0x0280)

Design configuration 1

Symbol	Bit range	R/W	Description
GEM_DBWDEF	27-25	R	Default data bus width?
GEM_IRQCOR	23	R	IRQ clear on read. 0=clear on write 1=clear on read
GEM_NO_PCS	0	R	PCS not implemented?

15.5.1.110. DESIGN_CFG2 (0x0284)

Design configuration 2

Symbol	Bit range	R/W	Description
reserved	31-30	R	Reserved, read as zero.
gem_tx_pbuf_addr	29-26	R	Takes the value of the `gem_tx_pbuf_addr DEFINE. Max address bits for Tx packet buffer (10-bits for maximum 4 kB buffer).
gem_rx_pbuf_addr	25-22	R	Takes the value of the `gem_rx_pbuf_addr DEFINE. Max address bits for Rx packet buffer (10-bits for maximum 4 kB buffer).
gem_tx_pkt_buffer	21	R	Takes the value of the `gem_tx_pkt_buffer DEFINE.
gem_rx_pkt_buffer	20	R	Takes the value of the `gem_rx_pkt_buffer DEFINE.
gem_hprot_value	19-16	R	Takes the value of the `gem_hprot_value DEFINE.
gem_jumbo_max_length	15-0	R	Takes the value of the `gem_jumbo_max_length DEFINE. Maximum length of jumbo frames accepted by receiver.

15.5.1.111. DESIGN_CFG3 (0x0288)

Design configuration 3

Symbol	Bit range	R/W	Description
gem_rx_base2_fifo_size	31-16	R	Takes the value of the `gem_rx_base2_fifo_size DEFINE. Base-2 equivalent of `gem_rx_fifo_size
gem_rx_fifo_size	15-0	R	Takes the value of the `gem_rx_fifo_size DEFINE. Set the size of the small Rx FIFO for grant latency.

15.5.1.112. DESIGN_CFG4 (0x028c)

Design configuration 4

Symbol	Bit range	R/W	Description
gem_tx_base2_fifo_size	31-16	R	Takes the value of the `gem_tx_base2_fifo_size DEFINE. Base-2 equivalent of `gem_tx_fifo_size.
gem_tx_fifo_size	15-0	R	Takes the value of the `gem_tx_fifo_size DEFINE. Set the size of the small TX FIFO for grant latency

15.5.1.113. DESIGN_CFG5 (0x0290)

Design configuration 5

Symbol	Bit range	R/W	Description
reserved	31-29	R	Reserved, read as zero.
gem_tsu_clk	28	R	Takes the value of the `gem_tsu_clk DEFINE. 1588 Time Stamp Unit clock sourced from pclk rather than independent tsu_clk.
gem_rx_buffer_length_def	27-20	R	Takes the value of the `gem_rx_buffer_length_def DEFINE. Set the default buffer length used by Rx DMA.
gem_tx_pbuf_size_def	19	R	Takes the value of the `gem_tx_pbuf_size_def DEFINE.
gem_rx_pbuf_size_def	18-17	R	Takes the value of the `gem_rx_pbuf_size_def DEFINE.
gem_endian_swap_def	16-15	R	Takes the value of the `gem_endian_swap_def DEFINE. Default values for descriptor endianess swap and data endianess swap.
gem_mdc_clock_div	14-12	R	Takes the value of the `gem_mdc_clock_div DEFINE. Set default MDC clock divisor (can still be programmed)
gem_dma_bus_width	11-10	R	Takes the value of the `gem_dma_bus_width_def DEFINE.
gem_phy_ident	9	R	Takes the value of the `gem_phy_ident DEFINE. Only used in PCS.
gem_tsu	8	R	Takes the value of the `gem_tsu DEFINE. Include support for 1588 Time Stamp Unit.
gem_tx_fifo_cnt_width	7-4	R	Takes the value of the `gem_tx_fifo_cnt_width DEFINE. Width for `gem_tx_fifo_size
gem_rx_fifo_cnt_width	3-0	R	Takes the value of the `gem_rx_fifo_cnt_width DEFINE. Width for `gem_rx_fifo_size.

15.5.1.114. DESIGN_CFG6 (0x0294)

Design configuration 6

Symbol	Bit range	R/W	Description
GEM_PBUF_LSO	27	R	?
GEM_DAW64	23	R	?

15.5.1.115. SPEC5_ADD_BOT ~ SPEC32_ADD_BOT (0x300 ~ 0x3d8)

Least significant part of the specific addresses 5~32.

When one of these registers is written, the corresponding address match is disabled. To set a new address and enable matching, set the SPECx_ADD_BOT register first and the SPECx_ADD_TOP last.

Offset	Register	Description
0x300	SPEC5_ADD_BOT	Specific address 5 bottom
0x308	SPEC6_ADD_BOT	Specific address 6 bottom
0x310	SPEC7_ADD_BOT	Specific address 7 bottom
0x318	SPEC8_ADD_BOT	Specific address 8 bottom
0x320	SPEC9_ADD_BOT	Specific address 9 bottom
0x328	SPEC10_ADD_BOT	Specific address 10 bottom
0x330	SPEC11_ADD_BOT	Specific address 11 bottom
0x338	SPEC12_ADD_BOT	Specific address 12 bottom
0x340	SPEC13_ADD_BOT	Specific address 13 bottom
0x348	SPEC14_ADD_BOT	Specific address 14 bottom
0x350	SPEC15_ADD_BOT	Specific address 15 bottom
0x358	SPEC16_ADD_BOT	Specific address 16 bottom
0x360	SPEC17_ADD_BOT	Specific address 17 bottom
0x368	SPEC18_ADD_BOT	Specific address 18 bottom
0x370	SPEC19_ADD_BOT	Specific address 19 bottom
0x378	SPEC20_ADD_BOT	Specific address 20 bottom
0x380	SPEC21_ADD_BOT	Specific address 21 bottom
0x388	SPEC22_ADD_BOT	Specific address 22 bottom
0x390	SPEC23_ADD_BOT	Specific address 23 bottom
0x398	SPEC24_ADD_BOT	Specific address 24 bottom
0x3a0	SPEC25_ADD_BOT	Specific address 25 bottom
0x3a8	SPEC26_ADD_BOT	Specific address 26 bottom
0x3b0	SPEC27_ADD_BOT	Specific address 27 bottom
0x3b8	SPEC28_ADD_BOT	Specific address 28 bottom
0x3c0	SPEC29_ADD_BOT	Specific address 29 bottom
0x3c8	SPEC30_ADD_BOT	Specific address 30 bottom
0x3d0	SPEC31_ADD_BOT	Specific address 31 bottom
0x3d8	SPEC32_ADD_BOT	Specific address 32 bottom

Symbol	Bit range	R/W	Description
ADD_BOT	31-0	RW	Least significant 32 bits of the destination address.

15.5.1.116. SPEC5_ADD_TOP ~ SPEC32_ADD_TOP (0x304 ~ 0x3dc)

Most significant part of the specific addresses 5~32.

When one of these registers is written, the corresponding address match is enabled. That means you must write to SPECx_ADD_BOT before SPECx_ADD_TOP in order to enable matching on the written address.

Offset	Register	Description
0x304	SPEC5_ADD_TOP	Specific address 5 top
0x30c	SPEC6_ADD_TOP	Specific address 6 top
0x314	SPEC7_ADD_TOP	Specific address 7 top
0x31c	SPEC8_ADD_TOP	Specific address 8 top
0x324	SPEC9_ADD_TOP	Specific address 9 top
0x32c	SPEC10_ADD_TOP	Specific address 10 top
0x334	SPEC11_ADD_TOP	Specific address 11 top
0x33c	SPEC12_ADD_TOP	Specific address 12 top
0x344	SPEC13_ADD_TOP	Specific address 13 top
0x34c	SPEC14_ADD_TOP	Specific address 14 top
0x354	SPEC15_ADD_TOP	Specific address 15 top
0x35c	SPEC16_ADD_TOP	Specific address 16 top
0x364	SPEC17_ADD_TOP	Specific address 17 top
0x36c	SPEC18_ADD_TOP	Specific address 18 top
0x374	SPEC19_ADD_TOP	Specific address 19 top
0x37c	SPEC20_ADD_TOP	Specific address 20 top
0x384	SPEC21_ADD_TOP	Specific address 21 top
0x38c	SPEC22_ADD_TOP	Specific address 22 top
0x394	SPEC23_ADD_TOP	Specific address 23 top
0x39c	SPEC24_ADD_TOP	Specific address 24 top
0x3a4	SPEC25_ADD_TOP	Specific address 25 top
0x3ac	SPEC26_ADD_TOP	Specific address 26 top
0x3b4	SPEC27_ADD_TOP	Specific address 27 top
0x3bc	SPEC28_ADD_TOP	Specific address 28 top
0x3c4	SPEC29_ADD_TOP	Specific address 29 top
0x3cc	SPEC30_ADD_TOP	Specific address 30 top
0x3d4	SPEC31_ADD_TOP	Specific address 31 top
0x3dc	SPEC32_ADD_TOP	Specific address 32 top

Symbol	Bit range	R/W	Description
ENABLE (TODO: check)	31	W	Enable matching on this address
reserved	31-16	R	Reserved, read as zero.
ADD_TOP	15-0	RW	Most significant 16 bits of the destination address.

15.5.1.117. CONTROL (0x07a0)

EMAC Control register

Symbol	Bit range	R/W	Description
reserved?	31-8	R	Reserved, read as zero
MODE	2-1	RW	0=MII/GMII/SGMII 1=RMII 2=RGMII 3=reserved
TWO_BYTES_IP_ALIGN	0	RW	Align something on 16 bit boundary?

15.6. GPI

Generic Packet Interface?

The GPI is the interface between memory and a peripheral. For EGPIs, that peripheral is an EMAC block (ethernet MAC). For HGPI, it is the HIF.

On the Rx path, the GPI reads packets from the peripheral, allocates one or more buffers depending on the size of the packet, and writes data and metadata into those buffers.

The GPI can use either DDR buffers, LMEM buffers, or both, depending on the configuration in GPI_RX_CONFIG.

On the Tx path, TODO.

15.6.1. GPI Rx buffer format

Large packets are split into fragments; each fragment is stored in its own allocated buffer, and starts with a header indicating where the next fragment is located. The header of the first fragment contains the packet metadata, such as packet length. That metadata is not repeated in the next segments. Also, the header is not written at all in the last fragment (it contains whatever garbage was last written there), so you must rely on the packet length from the header of the first fragment to know when you have reached the last fragment.

When both LMEM and DDR buffers are used, the first fragment is always stored in LMEM for fast processing by the PEs, while the next fragments are stored in DDR buffers. Also, in that mode of operation, at least one DDR buffer is allocated, even if the packet is small enough to be entirely stored in a single LMEM buffer; that DDR buffer will not be used by the GPI in that case.

GPI Rx fragments are stored into memory in the following format.

Offset	Size	Description
0x0	HDR_SIZE	Fragment Rx header
HDR_SIZE	DATA_OFFSET - HDR_SIZE	Free space for PE use
DATA_OFFSET	BUF_SIZE - DATA_OFFSET	Fragment data

HDR_SIZE, BUF_SIZE and DATA_OFFSET can be configured using registers HDR_SIZE, BUF_SIZE, DDR_DATA_OFFSET and LMEM_DATA_OFFSET.

15.6.1.1. GPI Rx fragment header

Byte order is big-endian.

Name	Offset	Size	Description
next_ptr	0x0	4	Pointer to the buffer containing the next fragment of the packet data that didn't fit into this buffer. Not written in last fragment.
length	0x4	2	(First fragment only) Total packet length. Depending on the GEMAC configuration, it may include the FCS.
phyno	0x6	2	(First fragment only) Input physical port number. 0=EGPI1, 1=EGPI2, other values unknown
status	0x8	4	(First fragment only) GEMAC status bits [63:32]
status2	0xc	4	(First fragment only) GEMAC status bits [31:0]

GEMAC status bits:

Name	Bit range	Description
OVERFLOW_ERR?	60	?
UDP_CHECKSUM_CORRECT?	59	UDP checksum is correct?
TCP_CHECKSUM_CORRECT?	58	TCP checksum is correct?
IP_CHECKSUM_CORRECT?	57	IP checksum is correct?
UNICAST_HASH_MATCH?	56	Destination matches unicast hash
CUMULATIVE_ARC_HIT?	55	?
MC_HASH_MATCH?	54	Destination matches multicast hash
CODE_ERR?	53	?
TOO_LONG_ERR?	52	?
TOO_SHORT_ERR?	51	?
CRC_ERR?	50	?
LENGTH_ERR?	49	?
CUMULATIVE_ERR? (also called BAD_FRAME_ERR)	48	?
SPEC32_ADD_MATCH	31	Destination address matches the one programmed in SPEC32_ADD_[BOT\|TOP] registers
SPEC31_ADD_MATCH	30	Destination address matches the one programmed in SPEC31_ADD_[BOT\|TOP] registers
SPEC30_ADD_MATCH	29	Destination address matches the one programmed in SPEC30_ADD_[BOT\|TOP] registers
SPEC29_ADD_MATCH	28	Destination address matches the one programmed in SPEC29_ADD_[BOT\|TOP] registers
SPEC28_ADD_MATCH	27	Destination address matches the one programmed in SPEC28_ADD_[BOT\|TOP] registers
SPEC27_ADD_MATCH	26	Destination address matches the one programmed in SPEC27_ADD_[BOT\|TOP] registers
SPEC26_ADD_MATCH	25	Destination address matches the one programmed in SPEC26_ADD_[BOT\|TOP] registers
SPEC25_ADD_MATCH	24	Destination address matches the one programmed in SPEC25_ADD_[BOT\|TOP] registers
SPEC24_ADD_MATCH	23	Destination address matches the one programmed in SPEC24_ADD_[BOT\|TOP] registers
SPEC23_ADD_MATCH	22	Destination address matches the one programmed in SPEC23_ADD_[BOT\|TOP] registers
SPEC22_ADD_MATCH	21	Destination address matches the one programmed in SPEC22_ADD_[BOT\|TOP] registers
SPEC21_ADD_MATCH	20	Destination address matches the one programmed in SPEC21_ADD_[BOT\|TOP] registers
SPEC20_ADD_MATCH	19	Destination address matches the one programmed in SPEC20_ADD_[BOT\|TOP] registers
SPEC19_ADD_MATCH	18	Destination address matches the one programmed in SPEC19_ADD_[BOT\|TOP] registers
SPEC18_ADD_MATCH	17	Destination address matches the one programmed in SPEC18_ADD_[BOT\|TOP] registers
SPEC17_ADD_MATCH	16	Destination address matches the one programmed in SPEC17_ADD_[BOT\|TOP] registers
SPEC16_ADD_MATCH	15	Destination address matches the one programmed in SPEC16_ADD_[BOT\|TOP] registers
SPEC15_ADD_MATCH	14	Destination address matches the one programmed in SPEC15_ADD_[BOT\|TOP] registers
SPEC14_ADD_MATCH	13	Destination address matches the one programmed in SPEC14_ADD_[BOT\|TOP] registers
SPEC13_ADD_MATCH	12	Destination address matches the one programmed in SPEC13_ADD_[BOT\|TOP] registers
SPEC12_ADD_MATCH	11	Destination address matches the one programmed in SPEC12_ADD_[BOT\|TOP] registers
SPEC11_ADD_MATCH	10	Destination address matches the one programmed in SPEC11_ADD_[BOT\|TOP] registers
SPEC10_ADD_MATCH	9	Destination address matches the one programmed in SPEC10_ADD_[BOT\|TOP] registers
SPEC9_ADD_MATCH	8	Destination address matches the one programmed in SPEC9_ADD_[BOT\|TOP] registers
SPEC8_ADD_MATCH	7	Destination address matches the one programmed in SPEC8_ADD_[BOT\|TOP] registers
SPEC7_ADD_MATCH	6	Destination address matches the one programmed in SPEC7_ADD_[BOT\|TOP] registers
SPEC6_ADD_MATCH	5	Destination address matches the one programmed in SPEC6_ADD_[BOT\|TOP] registers
SPEC5_ADD_MATCH	4	Destination address matches the one programmed in SPEC5_ADD_[BOT\|TOP] registers
SPEC4_ADD_MATCH	3	Destination address matches the one programmed in SPEC4_ADD_[BOT\|TOP] registers
SPEC3_ADD_MATCH	2	Destination address matches the one programmed in SPEC3_ADD_[BOT\|TOP] registers
SPEC2_ADD_MATCH	1	Destination address matches the one programmed in SPEC2_ADD_[BOT\|TOP] registers
SPEC1_ADD_MATCH	0	Destination address matches the one programmed in SPEC1_ADD_[BOT\|TOP] registers

15.6.2. GPI Tx buffer format

15.6.2.1. GPI Tx pre-header

Byte order is big-endian.

Name	Offset	Size	Description
start_data_off	0x0	1	Packet data start offset, relative to the start of this pre-header.
start_buf_off	0x1	1	This Tx pre-header start, relative to the start of the DDR buffer.
pkt_length	0x2	2	Total packet length
act_phyno	0x4	1	action / PHY number. 7-4: action low nibble 3-0: PHY number
queueno	0x5	1	action / queue number. 7-4: action high nibble 3-0: queue number
unused	0x6	2	Unused

Action bitfield:

Name	Bit range	Description
IPCHKSUM_REPLACE	6
DONT_FREE_BUFFER	5	Do not free the buffer after Tx completion
VLAN_REPLACE	3
TCPCHKSUM_REPLACE	2
VLAN_ADD	1
SRC_MAC_REPLACE	0

15.6.3. GPI registers

GPI instance	Base offset in CBUS
EGPI1	0x210000
EGPI2	0x230000
HGPI	0x290000
EGPI3	0x340000

GPI	Associated 'PHY'
EGPI1	EMAC1
EGPI2	EMAC2
EGPI3	EMAC3
HGPI	HIF

Symbol	Offset	Description
VERSION	0x000	GPI silicon revision register
CTRL	0x004	GPI control register
RX_CONFIG	0x008	GPI Rx config register
HDR_SIZE	0x00c	GPI header size register
BUF_SIZE	0x010	GPI buffer size register
LMEM_ALLOC_ADDR	0x014	GPI LMEM alloc address register
LMEM_FREE_ADDR	0x018	GPI LMEM free address register
DDR_ALLOC_ADDR	0x01c	GPI DDR alloc address register
DDR_FREE_ADDR	0x020	GPI DDR free address register
CLASS_ADDR	0x024	GPI CLASS address register
DRX_FIFO	0x028
TRX_FIFO	0x02c
INQ_PKTPTR	0x030	GPI packet IN Queue FIFO
DDR_DATA_OFFSET	0x034	GPI data offset for DDR packets
LMEM_DATA_OFFSET	0x038	GPI data offset for LMEM packets
TMLF_TX	0x04c
DTX_ASEQ	0x050
FIFO_STATUS	0x054	GPI FIFO status register
FIFO_DEBUG	0x058	GPI FIFO debug register
TX_PAUSE_TIME	0x05c	GPI Tx pause time register
LMEM_SEC_BUF_DATA_OFFSET	0x060	?
DDR_SEC_BUF_DATA_OFFSET	0x064	?
TOE_CHKSUM_EN	0x068
OVERRUN_DROPCNT	0x06c	GPI dropped packets counter register

15.6.3.1. VERSION (GPI_BASE + 0x000)

GPI silicon revision. 0x50 on my c2k chip.

Symbol	Bit range	R/W	Description
VERSION	?-0	R	GPI silicon revision

15.6.3.2. CTRL (GPI_BASE + 0x004)

GPI control register. The ENABLE bit must be set prior attempting to access the other GPI registers (except GPI_VERSION), otherwise the transaction may hang forever (or until the watchdog kicks in).

Performing a software reset will not reset the value of the configuration registers, only the internal state will be cleared.

Symbol	Bit range	R/W	Description
SW_RESET	1	RW	Perform software reset. Self-clearing.
ENABLE	0	RW	GPI enable. 0=disable 1=enable

15.6.3.3. RX_CONFIG (GPI_BASE + 0x008)

Rx configuration register.

Depending on their size, the packets may be written to LMEM for small packets, or DDR for larger ones.

Symbol	Bit range	R/W	Description
LMEM_RTRY_CNT	31-16	RW	LMEM write retry counter. Typical value is 0x40.
DDR_BUF_EN	1	RW	Enable use of buffers in DDR
LMEM_BUF_EN	0	RW	Enable use of buffers in LMEM

15.6.3.4. HDR_SIZE (GPI_BASE + 0x00c)

Header size configuration register.

Depending on whether packets are written to DDR or LMEM, the size of the header may differ. This register allows configuration of the header size for LMEM and DDR buffers.

Symbol	Bit range	R/W	Description
DDR_HDR_SIZE	31-16	RW	Header size for buffers in DDR. Typical value: 0x100
LMEM_HDR_SIZE	15-0	RW	Header size for buffers in LMEM. Typical value: 0x10

15.6.3.5. BUF_SIZE (GPI_BASE + 0x010)

Buffer size configuration register.

Depending on whether packets are written to DDR or LMEM, the size of the buffer may differ. This register allows configuration of the buffer size for LMEM and DDR buffers. The header size is included in the buffer size.

Symbol	Bit range	R/W	Description
DDR_BUF_SIZE	31-16	RW	Size of DDR buffers. Typical value: 0x800
LMEM_BUF_SIZE	15-0	RW	Size of LMEM buffers Typical value: 0x80

15.6.3.6. LMEM_ALLOC_ADDR (GPI_BASE + 0x014)

Address in the PE address space of the BMU_ALLOC_CTRL register of the BMU instance to use to allocate a new buffer in LMEM. Each read operation to the specified address must return the address of a newly-allocated buffer, or 0 if no buffer is available.

The buffer size for the BMU must be greater or equal to the one configured in the GPI.

Symbol	Bit range	R/W	Description
LMEM_ALLOC_ADDR	31-0	RW	Address of the BMU buffer allocation register to use for LMEM buffer allocation.

15.6.3.7. LMEM_FREE_ADDR (GPI_BASE + 0x018)

Address in the PE address space of the BMU_FREE_CTRL register of the BMU instance to used to manage buffers in LMEM. The addresses of buffers to free will be written at that address.

Symbol	Bit range	R/W	Description
LMEM_FREE_ADDR	31-0	RW	Address of the BMU buffer allocation register to use for LMEM buffer allocation.

15.6.3.8. DDR_ALLOC_ADDR (GPI_BASE + 0x01c)

Address in the PE address space of the BMU_ALLOC_CTRL register of the BMU instance to use to allocate a new buffer in DDR. Each read operation to the specified address must return the address of a newly-allocated buffer, or 0 if no buffer is available.

The buffer size for the BMU must be greater or equal to the one configured in the GPI.

Symbol	Bit range	R/W	Description
DDR_ALLOC_ADDR	31-0	RW	Address of the BMU buffer allocation register to use for DDR buffer allocation.

15.6.3.9. DDR_FREE_ADDR (GPI_BASE + 0x020)

Address in the PE address space of the BMU_FREE_CTRL register of the BMU instance to used to manage buffers in DDR. The addresses of buffers to free will be written at that address.

Symbol	Bit range	R/W	Description
DDR_FREE_ADDR	31-0	RW	Address of the BMU buffer allocation register to use for DDR buffer allocation.

15.6.3.10. CLASS_ADDR (GPI_BASE + 0x024)

Address in the PE address space of the INQ_PKTPTR FIFO register in the CLASS_CSR block.

The GPI will write the address of the first buffer to this location. This buffer follows the format defined in the GPI Rx buffer format.

Symbol	Bit range	R/W	Description
CLASS_ADDR	31-0	RW	Address of CLASS FIFO.

15.6.3.11. DRX_FIFO (GPI_BASE + 0x028)

Data? Rx FIFO depth? register?

Symbol	Bit range	R/W	Description
?	15-0	RW	? Default value: 0x80

15.6.3.12. TRX_FIFO (GPI_BASE + 0x02c)

? Rx FIFO depth? register?

Symbol	Bit range	R/W	Description
?	15-0	RW	? Default value: 0x80

15.6.3.13. INQ_PKTPTR (GPI_BASE + 0x030)

Tx packet descriptor address FIFO?

The address of the packet descriptor for the packet to send can be written into this register?

Symbol	Bit range	R/W	Description
PKTPTR	31-0	RW	Address of the Tx descriptor of the packet to send?

15.6.3.14. DDR_DATA_OFFSET (GPI_BASE + 0x034)

Offset in the DDR buffer where data starts.

Symbol	Bit range	R/W	Description
DATA_OFFSET	8-0	RW	Offset in the DDR buffer to the start of data region. Typical value: 0x100

15.6.3.15. LMEM_DATA_OFFSET (GPI_BASE + 0x038)

Offset in the LMEM buffer where data starts.

Symbol	Bit range	R/W	Description
DATA_OFFSET	7-0	RW	Offset in the LMEM buffer to the start of data region. Typical value: 0x10

15.6.3.16. TMLF_TX (GPI_BASE + 0x04c)

Something to do with TMU?

Symbol	Bit range	R/W	Description
TMLF_TXTHRES	7-0	RW	Something Tx threshold value. Typical value: 0xbc

15.6.3.17. DTX_ASEQ (GPI_BASE + 0x050)

Unknown.

Symbol	Bit range	R/W	Description
ASEQ_LEN	7-0	RW	Unknown. Typical value: 0x40. EGPI1 has value 0x50.

15.6.3.18. FIFO_STATUS (GPI_BASE + 0x054)

Some FIFO status register. Format unknown.

Symbol	Bit range	R/W	Description
STICK?	0	RW	Keep Tx on hold?

15.6.3.19. FIFO_DEBUG (GPI_BASE + 0x058)

Number of Tx/Rx packets/bytes queued in the FIFO.

Symbol	Bit range	R/W	Description
TX_PKTS	29-24	R	Tx packets
RX_PKTS	23-18	R	Rx packets
TX_BYTES	17-9	R	Tx bytes
RX_BYTES	8-0	R	Rx bytes

15.6.3.20. TX_PAUSE_TIME (GPI_BASE + 0x05c)

Tx pause frame time?

Symbol	Bit range	R/W	Description
TXPAUSE	15-0	RW	Tx pause time? Time unit unknown. Typical value: 0xffff

15.6.3.21. LMEM_SEC_BUF_DATA_OFFSET (GPI_BASE + 0x060)

Purpose unknown. Maybe offset to additional security context?

Symbol	Bit range	R/W	Description
DATA_OFFSET	15-0	RW	Typical value: 0x0

15.6.3.22. DDR_SEC_BUF_DATA_OFFSET (GPI_BASE + 0x064)

Purpose unknown. Maybe offset to additional security context?

Symbol	Bit range	R/W	Description
DATA_OFFSET	15-0	RW	Typical value: 0x0

15.6.3.23. TOE_CHKSUM_EN (GPI_BASE + 0x068)

Control some kind of checksum offloading?

Symbol	Bit range	R/W	Description
TOE_CHKSUM_EN	0	RW	Enable checksum ???

15.6.3.24. OVERRUN_DROPCNT (GPI_BASE + 0x06c)

Counter of dropped packets.

Symbol	Bit range	R/W	Description
DROPCNT	31-0	RW	Number of dropped packets.

15.7. Buffer Management Unit (BMU)

The buffer management unit (BMU) manages a buffer pool, allowing multiple peripherals to acquire and release buffers from the pool.

The base address of the buffer pool is configurable, as well as the buffer size. The number of buffers in the pool is configurable too, to a limit of 65535 buffers.

The BMU does not perform any DMA transfers; the state of the buffer pool is kept in an internal memory which can be cleared by a software reset.

Only up to 31 consecutive buffers may be allocated at any given time, if more are allocated, or if there is 31 buffers or more between the lowest and the highest allocated buffers, the BMU loses track of which buffers are allocated, causing an error in the free operation.

The BMU can generate interrupt requests to notify a PE of buffer pool state changes.

When a peripheral needs a buffer, it can allocate one by reading the BMU_ALLOC_CTRL register. If a buffer is available, its address will be returned and the BMU will mark this buffer as allocated. If no buffer is available, the address 0 will be returned.

To free a previously allocated buffer, the peripheral must write the buffer address into the BMU_FREE_CTRL register. If the peripheral attempts to double free a buffer, the address of the offending free operation will be stored in the BMU_FREE_ERR_ADDR register.

15.7.1. BMU registers

BMU instance	Base offset in CBUS
BMU1	0x240000
BMU2	0x250000

Symbol	Offset	Description
VERSION	0x000	BMU version register (reads 0x21 on my hardware)
CTRL	0x004	BMU control register (enable/reset)
UCAST_CONFIG	0x008	Number of buffers in the pool
UCAST_BASE_ADDR	0x00c	Base address to the buffer pool
BUF_SIZE	0x010	Size of one buffer in the pool
BUF_CNT	0x014	Not implemented? Always reads 0 and writes have no visible effect.
THRES	0x018	BMU buffer count threshold
INT_SRC	0x020	BMU interrupt source register
INT_ENABLE	0x024	BMU interrupt enable register
ALLOC_CTRL	0x030	Allocates one buffer from the pool
FREE_CTRL	0x034	Free one previously allocated buffer from the pool
FREE_ERR_ADDR	0x038	Address of buffer used in invalid free operation
CURR_BUF_CNT	0x03c	Number of buffers currently allocated
MCAST_CNT	0x040	Unknown
MCAST_ALLOC_CTRL	0x044	Unknown
REM_BUF_CNT	0x048	Number of remaining free buffers in the pool
LOW_WATERMARK	0x050	Low watermark value
HIGH_WATERMARK	0x054	High watermark value
INT_MEM_ACCESS	0x100	Internal memory access register

15.7.1.1. VERSION (BMU_BASE + 0x000)

BMU silicon revision. 0x21 on my c2k chip.

Symbol	Bit range	R/W	Description
VERSION	?-0	R	BMU silicon revision

15.7.1.2. CTRL (BMU_BASE + 0x004)

BMU control register. The ENABLE bit must be set prior attempting to access the other BMU registers (except BMU_VERSION), otherwise the transaction may hang forever (or until the watchdog kicks in).

Performing a software reset will not reset the value of the configuration registers, only the internal state will be cleared.

Symbol	Bit range	R/W	Description
SW_RESET	1	RW	Perform software reset. Self-clearing.
ENABLE	0	RW	BMU enable. 0=disable 1=enable

15.7.1.3. UCAST_CONFIG (BMU_BASE + 0x008)

Number of buffers in the pool.

Symbol	Bit range	R/W	Description
BUF_COUNT	15-0	RW	Total number of buffers in the pool.

15.7.1.4. UCAST_BASE_ADDR (BMU_BASE + 0x00c)

Base address of the buffer pool.

The BASE_ADDRESS value is only used to convert between the buffer index, used internally, and the full physical address, used for the BMU_ALLOC_CTRL and BMU_FREE_CTRL registers.

Symbol	Bit range	R/W	Description
BASE_ADDRESS	31-0	RW	Base address of the buffer pool.

15.7.1.5. BUF_SIZE (BMU_BASE + 0x010)

Size of one buffer in the pool.

The size in bytes is computed as follow:

BUF_SIZE_BYTES = 1 << BUF_SIZE

Symbol	Bit range	R/W	Description
BUF_SIZE	15-0	RW	Buffer size in powers of 2 (the BUF_SIZE value from above formula).

15.7.1.6. BUF_CNT (BMU_BASE + 0x014)

Unknown. Always reads 0. Writes have no visible effect.

15.7.1.7. THRES (BMU_BASE + 0x18)

Number of allocated buffer threshold at which an interrupt request should be generated.

Symbol	Bit range	R/W	Description
?	31-16	RW	Purpose unknown.
THRES	15-0	RW	An interrupt request is generated as long as the number of allocated buffer is greater or equal than THRES.

15.7.1.8. INT_SRC (BMU_BASE + 0x20)

Interrupt source pending and acknowledge register.

Reading from this register shows the pending interrupt requests.

Writing into this registers acknowledges the interrupt requests which have their bit set in the value written.

Symbol	Bit range	R/W	Description
?	8	RW	?
?	7	RW	?
?	6	RW	?
?	5	RW	?
INVALID_FREE	4	RW	Set when freeing an already free buffer, or freeing a buffer outside the pool.
THRES	3	RW	Set when the number of allocated buffers is greater or equal to the THRES value set in the BMU_THRES register.
FULL	2	RW	Set when all buffers are allocated.
EMPTY	1	RW	Set when no buffer is allocated.
?	0	RW	?

15.7.1.9. INT_ENABLE (BMU_BASE + 0x24)

Interrupt source enable register.

Symbol	Bit range	R/W	Description
?	8	RW	?
?	7	RW	?
?	6	RW	?
?	5	RW	?
INVALID_FREE	4	RW	See description in BMU_INT_SRC. 0=disable 1=enable
THRES	3	RW	See description in BMU_INT_SRC. 0=disable 1=enable
FULL	2	RW	See description in BMU_INT_SRC. 0=disable 1=enable
EMPTY	1	RW	See description in BMU_INT_SRC. 0=disable 1=enable
?	0	RW	?

15.7.1.10. ALLOC_CTRL (BMU_BASE + 0x30)

Buffer allocation register.

Reading from this register will allocate one buffer from the pool and return its address. If no free buffer is available, the value 0 is returned.

Symbol	Bit range	R/W	Description
BUF_ADDR	31-0	R	Address of the buffer just allocated.

15.7.1.11. FREE_CTRL (BMU_BASE + 0x34)

Buffer free register.

Writing an address into this register will free the previously-allocated buffer with that address.

If the address does not match any allocated buffer, an error will be reported via the INVALID_FREE interrupt source, and the offending address will be stored (at some point) in the BMU_FREE_ERR_ADDR register.

Symbol	Bit range	R/W	Description
BUF_ADDR	31-0	W	Address of the buffer to free.

15.7.1.12. FREE_ERR_ADDR (BMU_BASE + 0x38)

Buffer free error address register (buggy, see below).

This register should contain the address which was last written into BMU_FREE_CTRL if that address was not a valid allocated buffer.

It appears the hardware is buggy, and the correct value will not appear unless a few other invalid free attempts are made.

Symbol	Bit range	R/W	Description
BUF_ADDR	31-0	R	Address of the invalid buffer free attempt.

15.7.1.13. CURR_BUF_CNT (BMU_BASE + 0x3c)

Number of buffers currently allocated.

Symbol	Bit range	R/W	Description
BUF_CNT	15-0	R	Number of allocated buffers.

15.7.1.14. MCAST_CNT (BMU_BASE + 0x40)

Purpose unknown.

Symbol	Bit range	R/W	Description
?	2-0	RW	Unknown

15.7.1.15. MCAST_ALLOC_CTRL (BMU_BASE + 0x44)

Purpose unknown.

Symbol	Bit range	R/W	Description
?	31-0	R	Unknown

15.7.1.16. REM_BUF_CNT (BMU_BASE + 0x48)

Number of remaining free buffers in the pool.

Symbol	Bit range	R/W	Description
BUF_CNT	15-0	R	Number of free buffers.

15.7.1.17. LOW_WATERMARK (BMU_BASE + 0x50)

Purpose unknown.

Symbol	Bit range	R/W	Description
?	15-0	RW	Unknown. Default value: 0x0000

15.7.1.18. HIGH_WATERMARK (BMU_BASE + 0x54)

Purpose unknown.

Symbol	Bit range	R/W	Description
?	15-0	RW	Unknown. Default value: 0xffff

15.7.1.19. INT_MEM_ACCESS (BMU_BASE + 0x100)

Internal memory access register.

Symbol	Bit range	R/W	Description
?	31-0	R	Unknown. Value changes as buffers are allocated/freed.

15.8. Host Interface (HIF)

Manage and monitor a buffer descriptor pool and signal Rx/Tx events to the host using interrupt requests.

15.8.1. HIF registers

HIF instance	Base offset in CBUS
HIF	0x280000

Symbol	Offset	Description
VERSION	0x000	Version register (reads 0x10 on my hardware)
TX_CTRL	0x004	Tx control register
TX_CURR_BD_ADDR	0x008	Tx current buffer descriptor address
TX_ALLOC	0x00c	Tx allocation register?
TX_BDP_ADDR	0x010	Tx buffer descriptor pool address
TX_STATUS	0x014	Tx status register
RX_CTRL	0x020	Rx status register
RX_BDP_ADDR	0x024	Rx buffer descriptor pool address
RX_STATUS	0x030	Rx status
INT_SRC	0x034	Interrupt source status register
INT_ENABLE	0x038	Interrupt enable register
POLL_CTRL	0x03c	Polling control register
RX_CURR_BD_ADDR	0x040	Rx current buffer descriptor address
RX_ALLOC	0x044	Rx allocation register?
TX_DMA_STATUS	0x048	Tx DMA status register
RX_DMA_STATUS	0x04c	Rx DMA status register
INT_COAL	0x050	Interrupt coalesce control register

15.8.1.1. VERSION (HIF_BASE + 0x000)

HIF silicon revision. 0x10 on my c2k chip.

Symbol	Bit range	R/W	Description
VERSION	?-0	R	HIF silicon revision

15.8.1.2. TX_CTRL (HIF_BASE + 0x004)

Symbol	Bit range	R/W	Description
BDP_CH_START_WSTB	2	RW	Enable buffer descriptor pool start write strobe?
BDP_POLL_CTRL_EN	1	RW	Enable polling the buffer descriptor pool?
DMA_EN	0	RW	Enable DMA operation

15.8.1.3. TX_CURR_BD_ADDR (HIF_BASE + 0x008)

Symbol	Bit range	R/W	Description
CURR_BD_ADDR	31-0	R	Address of the current buffer descriptor

15.8.1.4. TX_ALLOC (HIF_BASE + 0x00c)

Purpose unknown.

Symbol	Bit range	R/W	Description
?	31-0	W	?

15.8.1.5. TX_BDP_ADDR (HIF_BASE + 0x010)

Get or set the address of the Tx buffer descriptor pool.

Writing a new value will reset the Tx current buffer descriptor.

Symbol	Bit range	R/W	Description
BDP_ADDR	31-0	RW	Address of the buffer descriptor pool

15.8.1.6. TX_STATUS (HIF_BASE + 0x014)

Contents unknown.

Symbol	Bit range	R/W	Description
BDP_CSR_TX_DMA_ACTV	16	R	Tx BDP busy (only in HIF_NOCPY?)
CTRL	15-0	R	Bit 31-16 from last Tx buffer descriptor control word

15.8.1.7. RX_CTRL (HIF_BASE + 0x020)

Symbol	Bit range	R/W	Description
BDP_CH_START_WSTB	2	RW	Enable buffer descriptor pool start write strobe? Self-clearing. Can be set to resume Rx in case of overrun.
BDP_POLL_CTRL_EN	1	RW	Enable polling the buffer descriptor pool?
DMA_EN	0	RW	Enable DMA operation

15.8.1.8. RX_BDP_ADDR (HIF_BASE + 0x024)

Get or set the address of the Rx buffer descriptor pool.

Writing a new value will reset the Rx current buffer descriptor.

Symbol	Bit range	R/W	Description
BDP_ADDR	31-0	RW	Address of the buffer descriptor pool

15.8.1.9. RX_STATUS (HIF_BASE + 0x030)

Contents unknown.

Symbol	Bit range	R/W	Description
BDP_CSR_RX_DMA_ACTV	16	R	Rx BDP busy
CTRL	15-0	R	Bit 31-16 from last Rx buffer descriptor control word

15.8.1.10. INT_SRC (HIF_BASE + 0x034)

Interrupt source status register.

An interrupt can be acknowledged by writing a value with the corresponding bit set.

Symbol	Bit range	R/W	Description
TXPKT_INT	4	R	Tx packet ??? interrupt
TXBD_INT	3	R	Tx buffer descriptor ??? interrupt
RXPKT_INT	2	R	Rx packet ??? interrupt
RXBD_INT	1	R	Rx buffer descriptor ??? interrupt
INT	0	R	Global interrupt?

15.8.1.11. INT_ENABLE (HIF_BASE + 0x038)

Interrupt source enable register.

Symbol	Bit range	R/W	Description
TXPKT_INT	4	RW	Tx packet ??? interrupt enable
TXBD_INT	3	RW	Tx buffer descriptor ??? interrupt enable
RXPKT_INT	2	RW	Rx packet ??? interrupt enable
RXBD_INT	1	RW	Rx buffer descriptor ??? interrupt enable
INT	0	RW	Global interrupt enable?

15.8.1.12. POLL_CTRL (HIF_BASE + 0x03c)

Polling control register

Symbol	Bit range	R/W	Description
31-16	RX_POLL_CTRL_CYCLE	RW	Number of pfe_sys clock cycles between Rx buffer descriptor pool poll attempts
15-0	TX_POLL_CTRL_CYCLE	RW	Number of pfe_sys clock cycles between Tx buffer descriptor pool poll attempts

15.8.1.13. RX_CURR_BD_ADDR (HIF_BASE + 0x040)

Symbol	Bit range	R/W	Description
CURR_BD_ADDR	31-0	R	Address of the current buffer descriptor

15.8.1.14. RX_ALLOC (HIF_BASE + 0x044)

Purpose unknown.

Symbol	Bit range	R/W	Description
?	31-0	W	?

15.8.1.15. TX_DMA_STATUS (HIF_BASE + 0x048)

Contents unknown.

Symbol	Bit range	R/W	Description

15.8.1.16. RX_DMA_STATUS (HIF_BASE + 0x04c)

Contents unknown.

Symbol	Bit range	R/W	Description
BUF_LEN	13-0	R	Length of last buffer transferred (same as the BUF_LEN value from the buffer descriptor)

15.8.1.17. INT_COAL (HIF_BASE + 0x050)

Interrupt coalesce control register

Symbol	Bit range	R/W	Description
31	INT_COAL_ENABLE	RW	Enable interrupt coalesce
30-0	TX_POLL_CTRL_CYCLE	RW	Minimum number of pfe_sys clock cycles between interrupts

15.9. TMU control and status registers (TMU_CSR)

Various register for TMU hardware.

15.9.1. TMU CSR registers

Base offset in CBUS	Seen from ARM	Seen from any PE
0x00310000	0x9c310000	0xc0310000

Registers:

Offset	Symbol	Description
0x0000	VERSION	TMU silicon revision
0x0004	INQ_WATERMARK
0x0008	PHY_INQ_PKTPTR
0x000c	PHY_INQ_PKTINFO
0x0010	PHY_INQ_FIFO_CNT
0x0014	SYS_GENERIC_CONTROL
0x0018	SYS_GENERIC_STATUS
0x001c	SYS_GEN_CON0
0x0020	SYS_GEN_CON1
0x0024	SYS_GEN_CON2
0x0028	SYS_GEN_CON3
0x002c	SYS_GEN_CON4
0x0030	TEQ_DISABLE_DROPCHK
0x0034	TEQ_CTRL
0x0038	TEQ_QCFG
0x003c	TEQ_DROP_STAT
0x0040	TEQ_QAVG
0x0044	TEQ_WREG_PROB
0x0048	TEQ_TRANS_STAT
0x004c	TEQ_HW_PROB_CFG0
0x0050	TEQ_HW_PROB_CFG1
0x0054	TEQ_HW_PROB_CFG2
0x0058	TEQ_HW_PROB_CFG3
0x005c	TEQ_HW_PROB_CFG4
0x0060	TEQ_HW_PROB_CFG5
0x0064	TEQ_HW_PROB_CFG6
0x0068	TEQ_HW_PROB_CFG7
0x006c	TEQ_HW_PROB_CFG8
0x0070	TEQ_HW_PROB_CFG9
0x0074	TEQ_HW_PROB_CFG10
0x0078	TEQ_HW_PROB_CFG11
0x007c	TEQ_HW_PROB_CFG12
0x0080	TEQ_HW_PROB_CFG13
0x0084	TEQ_HW_PROB_CFG14
0x0088	TEQ_HW_PROB_CFG15
0x008c	TEQ_HW_PROB_CFG16
0x0090	TEQ_HW_PROB_CFG17
0x0094	TEQ_HW_PROB_CFG18
0x0098	TEQ_HW_PROB_CFG19
0x009c	TEQ_HW_PROB_CFG20
0x00a0	TEQ_HW_PROB_CFG21
0x00a4	TEQ_HW_PROB_CFG22
0x00a8	TEQ_HW_PROB_CFG23
0x00ac	TEQ_HW_PROB_CFG24
0x00b0	TEQ_HW_PROB_CFG25
0x00b4	TDQ_IIFG_CFG
0x00b8	TDQ0_SCH_CTRL
0x00bc	LLM_CTRL
0x00c0	LLM_BASE_ADDR
0x00c4	LLM_QUE_LEN
0x00c8	LLM_QUE_HEADPTR
0x00cc	LLM_QUE_TAILPTR
0x00d0	LLM_QUE_DROPCNT
0x00d4	INT_EN
0x00d8	INT_SRC
0x00dc	INQ_STAT
0x00e0	CTRL	Main TMU control register
0x00e4	MEM_ACCESS_ADDR
0x00e8	MEM_ACCESS_WDATA
0x00ec	MEM_ACCESS_RDATA
0x00f0	PHY0_INQ_ADDR	PHY0 in queue address
0x00f4	PHY1_INQ_ADDR	PHY1 in queue address
0x00f8	PHY2_INQ_ADDR	PHY2 in queue address
0x00fc	PHY3_INQ_ADDR	PHY3 in queue address
0x0100	BMU_INQ_ADDR	BMU address to use to free packets
0x0104	TX_CTRL	Individual TMU PE enable register
0x0108	BUS_ACCESS_WDATA
0x010c	BUS_ACCESS
0x0110	BUS_ACCESS_RDATA
0x0114	PE_SYS_CLK_RATIO
0x0118	PE_STATUS
0x011c	TEQ_MAX_THRESHOLD
0x0134	PHY4_INQ_ADDR	PHY4 in queue address
0x0138	TDQ1_SCH_CTRL	Global scheduler enable for PHY1
0x013c	TDQ2_SCH_CTRL	Global scheduler enable for PHY2
0x0140	TDQ3_SCH_CTRL	Global scheduler enable for PHY3
0x0144	BMU_BUF_SIZE
0x0148	PHY5_INQ_ADDR	PHY5 in queue address
0x014c	?_STAT	Undocumented
0x0150	?	Undocumented
0x0154	?_STAT	Undocumented
0x0158	?	Undocumented
0x015c	?	Undocumented
0x0160	?	Undocumented
0x0164	?	Undocumented
0x0168	?	Undocumented
0x016c	?	Undocumented
0x0170	?	Undocumented
0x0174	?	Undocumented
0x0178	?	Undocumented

15.9.1.1. VERSION (0x0000)

TMU silicon revision.

Symbol	Bit range	R/W	Description
VERSION	31-0	R	TMU silicon revision. (0x01011231)

15.9.1.2. CTRL (0x00e0)

TMU reset register.

Symbol	Bit range	R/W	Description
LLM_INIT_DONE	9	R	Status bit set when the LMEM initialization is complete.
LLM_INIT	8	RW	Initialize the LMEM. LLM_INIT_DONE is set when init is complete.
MEM_INIT_DONE	7	R	Status bit set when the TMU PE memory initialization is complete.
MEM_INIT	6	RW	Initialize the PE memory. MEM_INIT_DONE is set when init is complete.
PE_RESET	5	RW	Reset all TMU PEs.
TDQ_RESET	4	RW	Reset TDQ block.
TEQ_RESET	3	RW	Reset TEQ block.
INQ_RESET	2	RW	Reset INQ block.
?	1	RW	Unknown.
SW_RESET	0	RW	Global software reset. All TMU blocks are reset.

15.9.1.3. TX_CTRL (0x0104)

Individual TMU PE enable register.

Symbol	Bit range	R/W	Description
TMU3	3	RW	Enable TMU3 PE core.
TMU3	2	RW	Enable TMU2 PE core.
TMU1	1	RW	Enable TMU1 PE core.
TMU0	0	RW	Enable TMU0 PE core.

15.10. Class control and status registers (CLASS_CSR)

Various control and registers for all the Class PEs.

15.10.1. Class CSR registers

Base offset in CBUS	Seen from ARM	Seen from any PE
0x00320000	0x9c320000	0xc0320000

Registers:

Offset	Symbol	Description
0x0000	VERSION	Class PE version
0x0004	TX_CTRL	Class PE core control
0x0010	INQ_PKTPTR
0x0014	HDR_SIZE
0x0020	PE0_QB_DM_ADDR0	DMEM address of 1st and 2nd buffers on QB side
0x0024	PE0_QB_DM_ADDR1	DMEM address of 3rd and 4th buffers on QB side
0x0060	PE0_RO_DM_ADDR0	DMEM address of 1st and 2nd buffers on RO side
0x0064	PE0_RO_DM_ADDR1	DMEM address of 3rd and 4th buffers on RO side
0x0100	MEM_ACCESS_ADDR	Class PE memory access command/address register
0x0104	MEM_ACCESS_WDATA	Data to write to Class PE memory
0x0108	MEM_ACCESS_RDATA	Data read from Class PE memory
0x0114	TM_INQ_ADDR
0x0118	PE_STATUS
0x011c	PHY1_RX_PKTS
0x0120	PHY1_TX_PKTS
0x0124	PHY1_LP_FAIL_PKTS
0x0128	PHY1_INTF_FAIL_PKTS
0x012c	PHY1_INTF_MATCH_PKTS
0x0130	PHY1_L3_FAIL_PKTS
0x0134	PHY1_V4_PKTS
0x0138	PHY1_V6_PKTS
0x013c	PHY1_CHKSUM_ERR_PKTS
0x0140	PHY1_TTL_ERR_PKTS
0x0144	PHY2_RX_PKTS
0x0148	PHY2_TX_PKTS
0x014c	PHY2_LP_FAIL_PKTS
0x0150	PHY2_INTF_FAIL_PKTS
0x0154	PHY2_INTF_MATCH_PKTS
0x0158	PHY2_L3_FAIL_PKTS
0x015c	PHY2_V4_PKTS
0x0160	PHY2_V6_PKTS
0x0164	PHY2_CHKSUM_ERR_PKTS
0x0168	PHY2_TTL_ERR_PKTS
0x016c	PHY3_RX_PKTS
0x0170	PHY3_TX_PKTS
0x0174	PHY3_LP_FAIL_PKTS
0x0178	PHY3_INTF_FAIL_PKTS
0x017c	PHY3_INTF_MATCH_PKTS
0x0180	PHY3_L3_FAIL_PKTS
0x0184	PHY3_V4_PKTS
0x0188	PHY3_V6_PKTS
0x018c	PHY3_CHKSUM_ERR_PKTS
0x0190	PHY3_TTL_ERR_PKTS
0x0194	PHY1_ICMP_PKTS
0x0198	PHY1_IGMP_PKTS
0x019c	PHY1_TCP_PKTS
0x01a0	PHY1_UDP_PKTS
0x01a4	PHY2_ICMP_PKTS
0x01a8	PHY2_IGMP_PKTS
0x01ac	PHY2_TCP_PKTS
0x01b0	PHY2_UDP_PKTS
0x01b4	PHY3_ICMP_PKTS
0x01b8	PHY3_IGMP_PKTS
0x01bc	PHY3_TCP_PKTS
0x01c0	PHY3_UDP_PKTS
0x01c4	PHY4_ICMP_PKTS
0x01c8	PHY4_IGMP_PKTS
0x01cc	PHY4_TCP_PKTS
0x01d0	PHY4_UDP_PKTS
0x01d4	PHY4_RX_PKTS
0x01d8	PHY4_TX_PKTS
0x01dc	PHY4_LP_FAIL_PKTS
0x01e0	PHY4_INTF_FAIL_PKTS
0x01e4	PHY4_INTF_MATCH_PKTS
0x01e8	PHY4_L3_FAIL_PKTS
0x01ec	PHY4_V4_PKTS
0x01f0	PHY4_V6_PKTS
0x01f4	PHY4_CHKSUM_ERR_PKTS
0x01f8	PHY4_TTL_ERR_PKTS
0x0200	PE_SYS_CLK_RATIO	Core clock/bus clock ratio
0x0204	AFULL_THRES
0x0208	GAP_BETWEEN_READS
0x020c	MAX_BUF_CNT
0x0210	TSQ_FIFO_THRES
0x0214	TSQ_MAX_CNT
0x0218	IRAM_DATA_0
0x021c	IRAM_DATA_1
0x0220	IRAM_DATA_2
0x0224	IRAM_DATA_3
0x0228	BUS_ACCESS_ADDR	Class bus access command/address register
0x022c	BUS_ACCESS_WDATA	Data to write to Class bus
0x0230	BUS_ACCESS_RDATA	Data read from Class bus
0x0234	ROUTE_HASH_ENTRY_SIZE
0x0238	ROUTE_TABLE_BASE
0x023c	ROUTE_MULTI	Route table configuration
0x0240	SMEM_OFFSET
0x0244	LMEM_BUF_SIZE
0x0248	VLAN_ID
0x024c	BMU1_BUF_FREE
0x0250	USE_TMU_INQ
0x0254	VLAN_ID1
0x0258	BUS_ACCESS_BASE	High byte of bus access address
0x025c	HIF_PARSE
0x0260	HOST_PE0_GP	Host general purpose register for PE0
0x0264	PE0_GP	PE general purpose register for PE0
0x0268	HOST_PE1_GP	Host general purpose register for PE1
0x026c	PE1_GP	PE general purpose register for PE1
0x0270	HOST_PE2_GP	Host general purpose register for PE2
0x0274	PE2_GP	PE general purpose register for PE2
0x0278	HOST_PE3_GP	Host general purpose register for PE3
0x027c	PE3_GP	PE general purpose register for PE3
0x0280	HOST_PE4_GP	Host general purpose register for PE4
0x0284	PE4_GP	PE general purpose register for PE4
0x0288	HOST_PE5_GP	Host general purpose register for PE5
0x028c	PE5_GP	PE general purpose register for PE5
0x0290	PE_INT_SRC
0x0294	PE_INT_ENABLE
0x0298	TPID0_TPID1
0x029c	TPID2
0x02a0	L4_CHKSUM_ADDR
0x02a4	PE0_DEBUG
0x02a8	PE1_DEBUG
0x02ac	PE2_DEBUG
0x02b0	PE3_DEBUG
0x02b4	PE4_DEBUG
0x02b8	PE5_DEBUG
0x02bc	STATE

15.10.1.1. VERSION (0x0000)

Class PE block version

Symbol	Bit range	R/W	Description
VERSION	31-0	R	Class PE block version. (0x20)

15.10.1.2. TX_CTRL (0x0004)

Class PE core state control.

Symbol	Bit range	R/W	Description
CTRL	1-0	RW	Enable/reset PE cores. 0=disable 1=enable 2=software reset

15.10.1.3. MEM_ACCESS_ADDR (0x0100)

Class PE internal memory access command/address register.

This register allows indirect access to a PE's internal memory. Writing a command into this register will trigger a read or write operation at the requested address.

IMEM is only accessible when the Class cores are disabled (TX_CTRL set to 0). DMEM is always accessible.

Warning: The PFE core clock must be enabled using the PFE_CLK_CNTRL register prior performing indirect memory access using this register, otherwise the transaction will hang.

Symbol	Bit range	R/W	Description
csr_pe_mem_cmd	31	RW	Read or write command. 0=read 1=write
csr_pe_mem_wren	27-24	RW	Bit mask indicating which data bytes will be read/written, interpreted in big endian.
csr_pe_mem_addr	23-0	RW	PE memory address to read/write. Address should be on a word boundary.

csr_pe_mem_addr decoding:

Base offset	PE	Memory type	Size
0x008000	CLASS0	IMEM	0x8000
0x010000	CLASS0	DMEM	0x2000
0x108000	CLASS1	IMEM	0x8000
0x110000	CLASS1	DMEM	0x2000
0x208000	CLASS2	IMEM	0x8000
0x210000	CLASS2	DMEM	0x2000
0x308000	CLASS3	IMEM	0x8000
0x310000	CLASS3	DMEM	0x2000
0x408000	CLASS4	IMEM	0x8000
0x410000	CLASS4	DMEM	0x2000
0x508000	CLASS5	IMEM	0x8000
0x510000	CLASS5	DMEM	0x2000

15.10.1.4. MEM_ACCESS_WDATA (0x0104)

Class PE internal memory write data register. Contains the data to write when a write request is written into MEM_ACCESS_ADDR. Value is in big endian.

Symbol	Bit range	R/W	Description
WDATA	31-0	RW	Word to write into internal memory

15.10.1.5. MEM_ACCESS_RDATA (0x0108)

Class PE internal memory read data register. Contains the data read after writing a read request into MEM_ACCESS_ADDR. Value is in big endian.

Symbol	Bit range	R/W	Description
RDATA	31-0	RW	Word read from internal memory

15.10.1.6. PE_SYS_CLK_RATIO (0x0200)

Core clock/bus clock ratio.

Symbol	Bit range	R/W	Description
RATIO	1-0	RW	Core clock/system bus clock ratio. 0=1:1 1=2:1

15.10.1.7. BUS_ACCESS_ADDR (0x0228)

Class PE internal bus access command/address register.

This register allows indirect access to the Class bus. Writing a command into this register will trigger a read or write operation at the requested address.

Symbol	Bit range	R/W	Description
CMD	31	RW	Read of write command. 0=read 1=write
WIDTH	27-24	RW	Access width in bytes. 1=byte 2=hword 4=word.
ADDR	23-0	RW	Class bus address where the access will be performed. Bits 31-24 are stored in BUS_ACCESS_BASE.

15.10.1.8. BUS_ACCESS_WDATA (0x022c)

Data word to write during Class bus access write request started by a write in BUS_ACCESS_ADDR. Value is in big endian.

Symbol	Bit range	R/W	Description
WDATA	31-0	RW	Word to write to Class bus. Big endian.

15.10.1.9. BUS_ACCESS_RDATA (0x0230)

Data word read after a Class bus access read request started by a write in BUS_ACCESS_ADDR. Value is in big endian.

Symbol	Bit range	R/W	Description
RDATA	31-0	RW	Word read from Class bus. Big endian.

15.10.1.10. ROUTE_MULTI (0x023c)

Route table configuration.

Symbol	Bit range	R/W	Description
QB2BUS_LE	15	RW	Byte swap something?
HASH_TYPE	13-12	RW	Hash type: 0=normal 1=CRC port 2=CRC IP 3=CRC port+IP
CLASS_TOE	11	RW	?
ARC_HIT_CHECK_EN	7	RW	?
IP_ALIGNED	6	RW	?
HW_BRIDGE_FETCH	5	RW	?
HW_ROUTE_FETCH	3	RW	?
PHYNO_IN_HASH	1	RW	Include PHY number in hash?
TWO_LEVEL_ROUTE	0	RW	?

15.10.1.11. BUS_ACCESS_BASE (0x0258)

Symbol	Bit range	R/W	Description
BASE	31-24	RW	High byte of bus address used in indirect Class bus accesses

15.10.1.12. HIF_PARSE (0x025c)

Symbol	Bit range	R/W	Description
HIF_PKT_OFFST	4-1	RW	Offset of HIF metadata in packet?
HIF_PKT_CLASS_EN	0	RW	Enable interpretation of HIF metadata?

15.10.1.13. L4_CHKSUM_ADDR (0x02a0)

Symbol	Bit range	R/W	Description
IPV4_CHKSUM_DROP	9	RW	?
UDP_CHKSUM_DROP	1	RW	?
TCP_CHKSUM_DROP	0	RW	?

15.11. Host Interface no copy (HIF nocpy)

Manage and monitor a buffer descriptor pool and signal Rx/Tx events to the host using interrupt requests.

15.11.1. HIF_NOCPY buffer descriptor format

Byte order is little-endian.

Name	Offset	Size	Description
ctrl	0x0	4	Control word
status	0x4	4	Status word
data	0x8	4	Data address word
next	0xc	4	Address of next descriptor. Last descriptor should link back to the first one.

15.11.1.1. Buffer descriptor fields

Control word:

Name	Bit range	Description
DESC_EN	31	Descriptor is enabled
RTFETCH_DISABLE	27	? Only effective if LIFM is set.
BRFETCH_DISABLE	26	? Only effective if LIFM is set.
PARSE_DISABLE	25	Disable frame header parsing? Only effective if LIFM is set.
PKT_XFER	24	Packet was transferred (Rx/Tx done)?
LMEM_CPY	21	Only for HIF_NOCPY. Allocate a LMEM buffer and write stuff in it?
DIR	20	Direction 0=Tx 1=Rx
LAST_BD	19	Last buffer descriptor in the list?
LIFM	18	Last buffer in frame
PKT_INT_EN	17	Trigger interrupt when packet is sent on the wire?
CBD_INT_EN	16	Trigger interrupt when buffer starts being processed?
BUF_LEN	13-0	Length of associated buffer. Only used by HIF?

Status word:

Probably only valid in the HIF buffer descriptors, not in HIF_NOCPY.

Name	Bit range	Description
CHKSUM_EN	22	?
LE_DATA	21	?
PROC_ID	20-18	?
CONN_ID_EN	17	?
DIR_PROC_ID	16	?
CONN_ID	15-0	?

15.11.2. HIF_NOCPY registers

HIF_NOCPY instance	Base offset in CBUS
HIF_NOCPY	0x350000

Symbol	Offset	Description
VERSION	0x000	Silicon revision register (reads 0x10 on my hardware)
TX_CTRL	0x004	Tx control register
TX_CURR_BD_ADDR	0x008	Current Tx buffer descriptor address
TX_ALLOC	0x00c	Tx allocation register?
TX_BDP_ADDR	0x010	Tx buffer descriptor pool address
TX_STATUS	0x014	Tx status register
RX_CTRL	0x020	Rx status register
RX_BDP_ADDR	0x024	Rx buffer descriptor pool address
RX_STATUS	0x030	Rx status
INT_SRC	0x034	Interrupt source status register
INT_ENABLE	0x038	Interrupt enable register
POLL_CTRL	0x03c	Polling control register
RX_CURR_BD_ADDR	0x040	Current Rx buffer descriptor address
RX_ALLOC	0x044	Rx allocation register?
TX_DMA_STATUS	0x048	Tx DMA status register
RX_DMA_STATUS	0x04c	Rx DMA status register
RX_INQ0_PKTPTR	0x050
RX_INQ1_PKTPTR	0x054
TX_PORT_NO	0x060
LMEM_ALLOC_ADDR	0x064
CLASS_ADDR	0x068
TMU_PORT0_ADDR	0x070
TMU_PORT1_ADDR	0x074
TMU_PORT2_ADDR	0x07c
TMU_PORT3_ADDR	0x080
TMU_PORT4_ADDR	0x084
INT_COAL	0x090	Interrupt coalesce control register

15.11.2.1. VERSION (HIF_NOCPY_BASE + 0x000)

HIF_NOCPY silicon revision. 0x10 on my c2k chip.

Symbol	Bit range	R/W	Description
VERSION	?-0	R	HIF_NOCPY silicon revision

15.11.2.17. RX_INQ0_PKTPTR (HIF_NOCPY_BASE + 0x50)

Incoming packet pointer INQ0 FIFO.

Software configures TMU_CSR to deliver packets for PHY4 here.

Symbol	Bit range	R/W	Description
PKTPTR	31-0	RW	Pointer to received packet buffer

15.11.2.18. RX_INQ1_PKTPTR (HIF_NOCPY_BASE + 0x54)

Incoming packet pointer INQ1 FIFO.

Symbol	Bit range	R/W	Description
PKTPTR	31-0	RW	Pointer to received packet buffer

15.11.2.19. TX_PORT_NO (HIF_NOCPY_BASE + 0x60)

Hardware port number to use for Tx packets.

Unused code in driver suggests that a valid value could be 4 (TMU PHY4).

Symbol	Bit range	R/W	Description
PORT_NO	15-0	RW	Hardware port number to use in outgoing packets

15.11.2.20. LMEM_ALLOC_ADDR (HIF_NOCPY_BASE + 0x64)

Address of the BMU register to read to allocate a LMEM buffer.

Software would set it to BMU1 BMU_ALLOC_CTRL.

This is used only when a buffer descriptor has control flag LMEM_CPY set.

Symbol	Bit range	R/W	Description
ADDR	31-0	RW	Address to the BMU_ALLOC_CTRL register of the BMU managing LMEM buffer pool.

15.11.2.21. CLASS_ADDR (HIF_NOCPY_BASE + 0x68)

Probably unused.

15.11.2.22. TMU_PORT0_ADDR (HIF_NOCPY_BASE + 0x70)

Address of the TMU IN Queue FIFO.

Software would set it to the address of TMU PHY_INQ_PKTPTR.

Symbol	Bit range	R/W	Description
ADDR	31-0	RW	Address of the IN queue FIFO register of the TMU (or compatible) block.

15.11.2.23. TMU_PORT1_ADDR (HIF_NOCPY_BASE + 0x74)

Another address of the TMU IN Queue FIFO.

Appears unused.

15.11.2.24. TMU_PORT2_ADDR (HIF_NOCPY_BASE + 0x78)

Another address of the TMU IN Queue FIFO.

Appears unused.

15.11.2.25. TMU_PORT3_ADDR (HIF_NOCPY_BASE + 0x7c)

Another address of the TMU IN Queue FIFO.

Appears unused.

15.11.2.26. TMU_PORT4_ADDR (HIF_NOCPY_BASE + 0x80)

Another address of the TMU IN Queue FIFO.

Appears unused.

15.11.2.27. INT_COAL (HIF_NOCPY_BASE + 0x090)

Same as HIF INT_COAL.

15.12. Util control and status registers (UTIL_CSR)

Various control and status registers for the Util PE.

15.12.1. Util CSR registers

Base offset in CBUS	Seen from ARM	Seen from any PE
0x00360000	0x9c360000	0xc0360000

Registers:

Offset	Symbol	Description
0x0000	VERSION	Util PE silicon revision
0x0004	TX_CTRL	Util PE core control
0x0010	INQ_PKTPTR
0x0014	HDR_SIZE
0x0020	PE0_QB_DM_ADDR0	DMEM address of 1st and 2nd buffers on QB side
0x0024	PE0_QB_DM_ADDR1	DMEM address of 3rd and 4th buffers on QB side
0x0060	PE0_RO_DM_ADDR0	DMEM address of 1st and 2nd buffers on RO side
0x0064	PE0_RO_DM_ADDR1	DMEM address of 3rd and 4th buffers on RO side
0x0100	MEM_ACCESS_ADDR	Util PE memory access command/address register
0x0104	MEM_ACCESS_WDATA	Data to write to Util PE memory
0x0108	MEM_ACCESS_RDATA	Data read from Util PE memory
0x0114	TM_INQ_ADDR
0x0118	PE_STATUS
0x0200	PE_SYS_CLK_RATIO	Core clock/bus clock ratio
0x0204	AFULL_THRES
0x0208	GAP_BETWEEN_READS
0x020c	MAX_BUF_CNT
0x0210	TSQ_FIFO_THRES
0x0214	TSQ_MAX_CNT
0x0218	IRAM_DATA_0
0x021c	IRAM_DATA_1
0x0220	IRAM_DATA_2
0x0224	IRAM_DATA_3
0x0228	BUS_ACCESS_ADDR	Util bus access command/address register
0x022c	BUS_ACCESS_WDATA	Data to write to Util bus
0x0230	BUS_ACCESS_RDATA	Data read from Util bus
0x0234	INQ_AFULL_THRES

15.13. CBUS general purpose timer (CBUS_GPT)

15.14. eSi-RISC architecture

The PE cores are implementation of an (32 bit?) eSi-RISC core configured in Harvard architecture.

15.15. Traffic/Time Management/Multiplexing Unit PE (TMU)

eSi-RISC core. Requires firmware.

The TMU does traffic shaping and scheduling.

15.16. Classifier PE (CLASS)

eSi-RISC core. Requires firmware.

15.17. UTIL PE (UTIL or UPE)

eSi-RISC core. Requires firmware.

Utility PE. Does all tasks that do not fit the other PEs.

16. USB 3.0 controller

The C2000 SoC integrates a DWC USB3.0 controller from Synopsys. It supports both device and host modes.

16.1. Memory map

Base address	0x9f000000

Range (offset from base)	Region size (w/o mirrors)	Description
0x00000-0x07fff	?	xHCI registers
0x00000-0x0001f	0x20	Host Controller Capability Registers
0x00020-0x0041f	0x400	Host Controller Operational Registers
0x00420-0x0042f	0x10	Host Controlelr Port Register Set
0x00440-0x0045f	0x8	Host Controller Runtime Registers
0x00460-0x0047f	0x20	Host Controller Interrupt Registers
0x00480-0x0087f	0x4	Host Controller Doorbell Register
0x00880-0x07fff	?	xHCI Extended Capabilities
0x0c100-0x0c6ff	?	Global Registers
0x0c700-0x0cbff	?	Device Registers
0x0cc00-0x0ccff	?	USB2.0 OTG and Battery Charger Registers
0x0cd00-0x0cfff	0x300	Unused/aliased
0x40000-0x7ffff	0x40000	Internal RAM 0 - Debug Access (256KB)
0x80000-0xbffff	0x40000	Internal RAM 1 - Debug Access (256KB)
0xc0000-0xfffff	0x40000	Internal RAM 2 - Debug Access (256KB)

16.1.1. xHCI registers

Refer to the xHCI specification.

16.1.2. Global register

Symbol	Offset	Description
GSBUSCFG0	0xc100
GSBUSCFG1	0xc104
GTXTHRCFG	0xc108
GRXTHRCFG	0xc10c
GCTL	0xc110
GEVTEN	0xc114
GSTS	0xc118
GSNPSID	0xc120
GGPIO	0xc124
GUID	0xc128
GUCTL	0xc12c
GBUSERRADDR_31_0	0xc130
GBUSERRADDR_63_32	0xc134
GPRTBITMAP_31_0	0xc138
GPRTBITMAP_63_32	0xc13c
GHWPARAMS0	0xc140
GHWPARAMS1	0xc144
GHWPARAMS2	0xc148
GHWPARAMS3	0xc14c
GHWPARAMS4	0xc150
GHWPARAMS5	0xc154
GHWPARAMS6	0xc158
GHWPARAMS7	0xc15c
GDBGFIFOSPACE	0xc160
GDBGLTSSM	0xc164
GDBGLNMCC	0xc168
GDBGBMU	0xc16c
GDBGLSPMUX	0xc170
GDBGLSP	0xc174
GDBGEPINFO0	0xc178
GDBGEPINFO1	0xc17c
GPRTBITMAP_HS_31_0	0xc180
GPRTBITMAP_HS_63_32	0xc184
GPRTBITMAP_FS_31_0	0xc188
GPRTBITMAP_FS_63_32	0xc18c
GUSB2PHYCFG_0	0xc200
GUSB2PHYCFG_x	0xc200 + (4 * x)
GUSB2PHYCFG_15	0xc23c
GUSB2I2CCTL_0	0xc240
GUSB2PHYCFG_x	0xc240 + (4 * x)
GUSB2I2CCTL_15	0xc27c
GUSB2PHYACC_0	0xc280
GUSB2PHYACC_x	0xc280 + (4 * x)
GUSB2PHYACC_15	0xc2bc
GUSB3PIPECTL_0	0xc2c0
GUSB3PIPECTL_x	0xc2c0 + (4 * x)
GUSB3PIPECTL_15	0xc2fc
GTXFIFOSIZ_0	0xc300
GTXFIFOSIZ_x	0xc300 + (4 * x)
GTXFIFOSIZ_31	0xc37c
GRXFIFOSIZ_0	0xc380
GRXFIFOSIZ_x	0xc380 + (4 * x)
GRXFIFOSIZ_31	0xc3fc
GEVNTADR_31_0_0	0xc400
GEVNTADR_63_32_0	0xc404
GEVNTSIZ_0	0xc408
GEVNTCOUNT_0	0xc40c
GEVNTADR_31_0_x	0xc400 + (0x10 * x)
GEVNTADR_63_32_x	0xc404 + (0x10 * x)
GEVNTSIZ_x	0xc408 + (0x10 * x)
GEVNTCOUNT_x	0xc40c + (0x10 * x)
GEVNTADR_31_0_31	0xc500
GEVNT_63_32_31	0xc504
GEVNTSIZ_31	0xc508
GEVNTCOUNT_31	0xc50c
GHWPARAMS8	0xc600

16.1.3. Device registers

16.1.4. USB 2.0 OTG and Battery Charger register

17. Expansion bus

The C2000 SoC features an expansion bus to add external peripherals such as ROM, NOR flash, NAND flash and custom devices.

To help handling NAND devices, a hardware ECC accelerator can be used to compute error correction code for the data flowing to/from the NAND device.

17.1. Memory map

Address space	Range
Expansion bus configuration registers (APB)	0x905a0000-0x905affff
Expansion bus address space (AXI slave interface and AHB bridge)	0xc0000000-0xcfffffff
CS0 slave address space	0xc0000000-0xc0ffffff
CS1 slave address space	0xc1000000-0xc1ffffff
CS2 slave address space	0xc2000000-0xc2ffffff
CS3 slave address space	0xc3000000-0xc3ffffff
CS4/NAND slave address space	0xc4000000-0xc4ffffff
ECC registers	0xcfff0000-0xcfffffff

17.2. Expansion bus control registers

Base address	0x905a0000

Symbol	Offset	Description
SW_RST	0x000	Software reset register
CS_EN	0x004	CS enable register
CS0_BASE	0x008	CS0 base address register
CS1_BASE	0x00c	CS1 base address register
CS2_BASE	0x010	CS2 base address register
CS3_BASE	0x014	CS3 base address register
CS4_BASE	0x018	CS4 base address register
CS0_SEG	0x01c	CS0 segment size register
CS1_SEG	0x020	CS1 segment size register
CS2_SEG	0x024	CS2 segment size register
CS3_SEG	0x028	CS3 segment size register
CS4_SEG	0x02c	CS4 segment size register
CS0_CFG	0x030	CS0 configuration register
CS1_CFG	0x034	CS1 configuration register
CS2_CFG	0x038	CS2 configuration register
CS3_CFG	0x03c	CS3 configuration register
CS4_CFG	0x040	CS4 configuration register
CS0_TMG1	0x044	CS0 timing register 1
CS1_TMG1	0x048	CS1 timing register 1
CS2_TMG1	0x04c	CS2 timing register 1
CS3_TMG1	0x050	CS3 timing register 1
CS4_TMG1	0x054	CS4 timing register 1
CS0_TMG2	0x058	CS0 timing register 2
CS1_TMG2	0x05c	CS1 timing register 2
CS2_TMG2	0x060	CS2 timing register 2
CS3_TMG2	0x064	CS3 timing register 2
CS4_TMG2	0x068	CS4 timing register 2
CS0_TMG3	0x06c	CS0 timing register 3
CS1_TMG3	0x070	CS1 timing register 3
CS2_TMG3	0x074	CS2 timing register 3
CS3_TMG3	0x078	CS3 timing register 3
CS4_TMG3	0x07c	CS4 timing register 3
CLOCK_DIV	0x080	Clock divider register
MFSM	0x100
CSFSM	0x104
WRSM	0x108
RDSM	0x10c

17.2.1. SW_RST (0x905a0000)

Expansion bus soft reset register.

When SW_RST bit is set, the expansion bus logic is reset synchronously. Configuration registers is not affected by the soft reset. The SW_RST bit self-clears when the reset is complete. Software should wait until SW_RST value is back to 0 before using the expansion bus.

Symbol	Bit range	R/W	Description
SW_RST	0	R?W	Write 1 to perform soft reset. Self-clearing.

17.2.2. CS_EN (0x905a0004)

Expansion bus chip select enable.

Symbol	Bit range	R/W	Description
CS4_EN	5	RW	Enable device with chip select 4
CS3_EN	4	RW	Enable device with chip select 3
CS2_EN	3	RW	Enable device with chip select 2
CS1_EN	2	RW	Enable device with chip select 1
CS0_EN	1	RW	Enable device with chip select 0
CLK_EN	0	RW	Enable expansion bus clock

17.2.3. CSx_BASE

Expansion bus chip select base address register.

Chip select	Register address
CS0	0x905a0008
CS1	0x905a000c
CS2	0x905a0010
CS3	0x905a0014
CS4	0x905a0018

Symbol	Bit range	R/W	Description
BASEADDR	27-0	RW	Base offset in the EXP AXI slave region.

17.2.4. CSx_SEG

Expansion bus chip select segment size register. FIXME: Not a size but region end address?

Chip select	Register address
CS0	0x905a001c
CS1	0x905a0020
CS2	0x905a0024
CS3	0x905a0028
CS4	0x905a002c

Symbol	Bit range	R/W	Description
SEG_SIZE	27-0	RW	Segment size of the EXP AXI slave region.

17.2.5. CSx_CFG

Expansion bus chip select enable.

Chip select	Register address
CS0	0x905a0030
CS1	0x905a0034
CS2	0x905a0038
CS3	0x905a003c
CS4	0x905a0040

Symbol	Bit range	R/W	Description
RDY_EDG	11	RW	`EXP_RDY` signal polarity
RDY_EN	10	RW	Wait `EXP_RDY` signal for read/write operation after address. 0=Ignore ready signal 1=Wait for ready signal
NAND_MODE	9	RW	NAND mode. Valid only for CS4. 0=Normal 1=NAND mode
DM_MODE	8	RW	Data mask mode.
STRB_MODE	7	RW	Strobe mode (R/W signal + strobe signal) 0=Normal 1=Strobe mode
ALE_MODE	6	RW	Address latch enable (address/data signals multiplexing) 0=Normal 1=ALE mode
RE_CMD_LVL	5	RW	Read enable signal polarity
WE_CMD_LVL	4	RW	Write enable signal polarity
CS_LEVEL	3	RW	Chip select signal polarity
MEM_BUS_SIZE	2-1	RW	Memory bus width. 0=8 bit 1=16 bit 2=32 bit 3=Reserved/unknown
?	0	?	Unknown

17.2.6. CSx_TMG1

Expansion bus chip select timings 1 configuration.

Chip select	Register address
CS0	0x905a0044
CS1	0x905a0048
CS2	0x905a004c
CS3	0x905a0050
CS4	0x905a0054

Symbol	Bit range	R/W	Description
?	31-0	?	Timing values. Used for NAND by IRB: 0x0a0a001a

17.2.7. CSx_TMG2

Expansion bus chip select timings 2 configuration.

Chip select	Register address
CS0	0x905a0058
CS1	0x905a005c
CS2	0x905a0060
CS3	0x905a0064
CS4	0x905a0068

Symbol	Bit range	R/W	Description
?	31-0	?	Timing values. Used for NAND by IRB: 0x05050202

17.2.8. CLOCK_DIV (0x905a0080)

EXPCLK clock divider register. When EXPCLK source is the AXI clock, the clock frequency is divided by the ratio from this register to form the final EXPCLK.

Maximum rate for EXPCLK is 66.6 MHz. Valid RATIO range is 3-15.

Symbol	Bit range	R/W	Description
RATIO	3-0	RW	EXPCLK clock divider ratio. 0-2=reserved 3-15=valid Default value on reset: 7

17.2.9. MFSM (0x905a0100)

17.2.10. CSFSM (0x905a0104)

17.2.11. WRSM (0x905a0108)

17.2.12. RDSM (0x905a010c)

17.3. Expansion bus ECC registers

Base address	0xcfff0000

Symbol	Offset	Description
SHIFT_EN_CFG	0x00
GEN_CFG	0x04	ECC general configuration register
TAG_CFG	0x08
INIT_CFG	0x0c
PRTY_OUT_SEL_CFG	0x10
POLY_START_CFG	0x14
CS_SEL_CFG	0x18
IDLE_STAT	0x1c
POLY_STAT	0x20
CORR_STAT	0x24
CORR_DONE_STAT	0x28
CORR_DATA_STAT	0x2c

17.3.1. SHIFT_EN_CFG (0xcfff0000)

Symbol	Bit range	R/W	Description
SHIFT_EN	0	RW	0=disable 1=enable

17.3.2. GEN_CFG (0xcfff0004)

ECC general configuration register.

Symbol	Bit range	R/W	Description
CODE_MODE	28	RW	0=BCH 1=Hamming
PRTY_MODE	24	RW	0=Symdrome generation 1=Parity word calculation
LVL	22-16	RW	ECC level. Accepted values: 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32
BLK_SIZE	10-0	RW	ECC block size in bytes. Maximum value is: `2048 - (1 + (14 * LVL) / 8)`

17.3.3. TAG_CFG (0xcfff0008)

17.3.4. INIT_CFG (0xcfff000c)

Symbol	Bit range	R/W	Description
INIT	0	RW	0=No effect 1=Reset parity module and latch configured values

17.3.5. PRTY_OUT_SEL_CFG (0xcfff0010)

Parity data out control register.

When parity data output is enabled, the data word in AHB write transactions is replaced by the parity data. So, to write parity data to NAND flash, write 1 to this register and perform as many dummy writes to the EXP bus CS4 region as there is parity data words.

Symbol	Bit range	R/W	Description
ENABLE	0	RW	0=do not change AHB write data 1=replace AHB write data with parity data

17.3.6. POLY_START_CFG (0xcfff0014)

Symbol	Bit range	R/W	Description
POLY_START	0	RW	0=No effect 1=Start correction operation

17.3.7. CS_SEL_CFG (0xcfff0018)

Symbol	Bit range	R/W
CS4_SEL	4	RW
CS3_SEL	3	RW
CS2_SEL	2	RW
CS1_SEL	1	RW
CS0_SEL	0	RW

17.3.8. IDLE_STAT (0xcfff001c)

Idle status register.

Symbol	Bit range	R/W	Description
IDLE	0	R	0=Busy 1=Idle

17.3.9. POLY_STAT (0xcfff0020)

Correction status register.

Symbol	Bit range	R/W	Description
UNCORR_ERR_HAMM	2	R	0=Nothing to report 1=Uncorrectable error in Hamming code mode
ERASED_PAGE	1	R	0=? 1=?
CORR_REQ	0	R	0=Ok 1=Correction required

17.3.10. CORR_STAT (0xcfff0024)

Symbol	Bit range	R/W	Description
UNCORR	24	R	0=Nothing to report 1=Uncorrectable error found
NUM_ERR	21-16	R	Number of errors found
TAG	15-0	R	?

17.3.11. CORR_DONE_STAT (0xcfff0028)

Symbol	Bit range	R/W	Description
DONE	0	R	0=Correction not done yet 1=Correction done

17.3.12. CORR_DATA_STAT (0xcfff002c)

In BCH mode:

Symbol	Bit range	R/W
BCH_VALID	31	R
BCH_INDEX	26-16	R
BCH	15-0	R

In Hamming mode:

Symbol	Bit range	R/W
HAMM_VALID	31	R
HAMM_INDEX	24-16	R
HAMM	7-0	R